JPH036691B2 - - Google Patents

Description

TECHNICAL FIELD The present invention relates to linear phase finite impulse response (FIR) digital filters.

[Technical background of the invention]

Linear phase digital filters can be designed to have a linear phase with respect to frequency, and are relatively easy to design, so they have become widely used.

A characteristic of a linear phase FIR digital filter is that its filter order is N, and the N impulse response sequences are h(0), h(1), h(2)...h(N-2), h(N- 1
), and if N is an odd number, h(0)=h(N-1), h(1)=h(N-
2)...h(N-3/2)=h(N+1/2), and if N is an even number, h(0)=h(N-1), h(1)=h(N-2)... h(
N/2-2)=h(N/2+2), h(N/2-1)=
h
(N/2+1), and it is generally known that h(n)=h(N-1-n) holds using a natural number n (0<n<N).

In other words, the impulse response train has symmetry about the center.

The system function of the FIR digital filter is Z
Using the complex variable Z of the transformation, H(z)= _N-1 〓 ⁿ⁼⁰ h(n) expressed as z ^-n , and h(n) with specific filter characteristics.
The coefficient sequence of is determined. Based on the coefficient sequence determined in this way, each coefficient data is stored in a storage circuit such as a ROM, but storing all coefficient data would require a large capacity storage circuit.

〔the purpose〕

The present invention makes use of the symmetry of the impulse response train of a linear phase finite impulse response digital filter, stores only the filter coefficients corresponding to half the impulse response train in a storage circuit, and reads them out using a reversible counter. The aim is to halve the storage capacity of the memory circuit.

〔Example〕

In FIG. 1, 1 is a first storage circuit which stores N encoded binary input data supplied from its input.
When the latest input data is stored in X(N-1), the data stored in X(0) before that input data is discarded, and N input data is stored. 2 is a second storage circuit consisting of ROM etc.;
Radical coefficient data H(0), H(1)...H(M-1), H(M
)
has been memorized. In this example, the filter order is set to N, and when N is an odd number, M=N/2-1, and when N is an even number, M=N/2. That is, only half of all coefficient data is stored in the storage circuit 2. 3 is a reversible counter for reading out the coefficient data, and 4 is a control circuit that performs up-down switching of the reversible counter 3, etc. A multiplier 5 multiplies input data and coefficient data. 6 is an adder, and 7 is an accumulator.

Next, the operation will be explained. The memory circuit 1 stores N pieces of input data X(0)...X(N-1), and each input data X(0)...X( N-1) and the coefficient data H(0) . . . H(M) in the storage circuit 2. During this product-sum calculation, the input is closed, and the circulation path 1a moves from X(0) to X(N
-1) is transferred by one data for each multiplication, and is sequentially supplied to the multiplier 5 so that each data is not lost. This order is
(0), X(1)...X(N-2), X(N-1). As this data is supplied, each coefficient data is read out from the storage circuit 2 as follows, and a product-sum calculation is performed.

The reading method is slightly different depending on whether the filter order N is an odd number or an even number, and the case where the filter order N is an odd number will be explained first. First, the coefficient data H of the reversible counter 3 is
It is set to address A (0) and counted up one by one in synchronization with the circulation of data in the memory circuit 1. As a result, coefficient data H(0)...H
(M) are sequentially read out in this order. When the reversible counter 3 counts the address (A+M) of the coefficient data H(M), a down mode designation output is generated from the control circuit 4, and the reversible counter 3 switches to down counting. Therefore, contrary to the above, the coefficient data H(M-1)...H(0) are read out in this order.

In this way, the coefficient data are H(0), H(1)...H(M
-1), H(M), H(M-1)...H(0) are supplied to the multiplier 5 in this order, and the corresponding input data X(0), X(1)...X(N-2 ) and X(N-1), respectively. FIG. 2 shows the operation up to this point. The above multiplication results are supplied to an adder 6, and all product-sum calculation results are output from an accumulator 7. This output Y is: Y= _N-1 〓 ⁿ⁼⁰ H(n)・X(2M-n)+H(M)・X(M)+ _N-1 〓 ⁿ⁼⁰ H(M-1-n)・Represented by X(M-1-n).

Next, a case where the filter order N is an even number will be explained. First, the reversible counter 3 is set to coefficient data H(0)
address A, and count up one by one in the same way as above. When the reversible counter 3 counts the address (A+M-1) of the coefficient data H(M-1), the clock pulse from the control circuit 4 stops by one pulse, and the contents of the reversible counter 3 become 1.
It will only be kept as is. From then on, the reversible counter 3 switches to the down mode and counts down one by one. As a result, the coefficient data are H(0), H(1)...H(M-2), H(M-
1), H(M-1), H(M-2)...H(1), H(0)
are sequentially read out in this order, and the corresponding input data X(0), X(1)...X(N-2), X(N-
1) respectively. FIG. 3 shows the operation up to this point. The multiplication results are sequentially added and output from the accumulator 7 in the same manner as above. This output Y is as follows: Y= _N-1 〓 ⁿ⁼⁰ H(n)・X(2M-1-n)+ _N-1 〓 ⁿ⁼⁰ H(M-1-n)・X(M-1- n).

As described above, the accumulator 7 obtains the product-sum operation result.

〔effect〕

According to the present invention, based on the symmetry of the impulse response train, when the filter order N is an odd number, h
(0), h(1)...up to h(N-1/2), and in the case of an even number, h (0), h(1)...up to h(N/2-1) 2
Since the binary coefficient data is stored in memory, each data is sequentially read out using a reversible counter, and then read out again in the reverse order and successively multiplied with the input data, the storage capacity of the binary coefficient data can be halved. ,
Moreover, the circuit configuration for read control can also be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are explanatory diagrams for explaining the operation. DESCRIPTION OF SYMBOLS 1...First memory circuit, 2...Second memory circuit, 3...Reversible counter, 4...Control circuit, 5...
Multiplier, 6...adder, 7...accumulator.

Claims (1)

[Scope of Claims] 1. A first storage circuit that stores a plurality of binary input data in a delayed manner, a second storage circuit that stores a plurality of binary coefficient data, and the binary input data and the binary coefficient data. If the system is equipped with an arithmetic circuit that performs a product-sum operation by sequentially multiplying and accumulating data, and the filter order is N, then the system function H(z) is calculated using the impulse response coefficient h(n). , H(z)= _N-1 〓 ⁿ⁼⁰ h(n)z ^-n , and the impulse response is a linear phase finite impulse response that satisfies h(n)=h(N-1-n). In the digital filter, based on the symmetry of the above impulse response, if the filter order N is an odd number, h(0), t(1)...h
Up to (N-1/2), h(0), h(1) for even numbers
... The binary coefficient data corresponding to up to h(N/2-1) are stored in the second storage circuit in this order, and each binary coefficient data in the second storage circuit is , h(0), h(1)...h(N-1/2), if N is an even number, h(0), h(1)...h
(N/2-1) in order according to the size of n of h(n), and then read each binary coefficient data as h(N-3/2) if N is an odd number. ) to h (0), and if N is even, h(N/2−
A reversible counter is provided to read out the values from 1) to h(0) again in the reverse order to the above, and each binary coefficient data from the second storage circuit and the first
A digital filter that performs a product-sum operation with binary input data from a storage circuit.