JPH036717A - information processing equipment - Google Patents

Abstract

PURPOSE:To easily reduce the power consumption by reducing the clock frequency of at least a circuit part which controls a display device. CONSTITUTION:A VRAM 13 connected to a screen I/F 12 has the largest power consumption. While the I/F 12 must work at all times to project the screens even when a CPU 10 performs nothing with a power supply applied to an information processor. Thus it is most effective to reduce the working frequency of the VRAM 13 in order to reduce the power consumption. For this purpose, the CLK frequency applied to the I/F 12 is reduced. As a result, the power consumption is reduced without deteriorating the performance of the information processor.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an information processing device with reduced power consumption.

[Prior Art] A conventional power consumption reduction mechanism in an information processing device changes components from components that consume a large amount of current to components that consume less current. For example, in logic IC, TTL
It was known to change from the original to a CMO3 component, or to lower the frequency of only the CPU clock signal.

[Problem to be solved by the invention] However, simply changing the currently used parts to parts that consume less power will still consume a lot of power for the entire information processing device. There is a problem of shortened lifespan.

In addition, as for the method of lowering the CPU clock frequency, the ratio of main memory access time to the actual use of the information processing device is generally not that high, so in reality, it is difficult to reduce the power consumption. The result is that it does not decrease. Also, lower the CPU clock frequency! 'The performance of the information processing device will be degraded.

Therefore, in order to solve these problems, it is an object of the present invention to provide an information processing device that reduces power consumption without degrading the performance of the information processing device.

[Means for Solving the Problems] The present invention provides a method for reducing power consumption in an information processing device including at least an arithmetic processing section, a main storage device, a memory control section, a display control section, a display device, and an external storage device. The information processing apparatus is characterized by comprising a mechanism for switching a clock signal of a circuit section that controls a display device of the information processing apparatus.

[Examples] Hereinafter, the present invention will be described in detail based on Examples. FIG. 1 is a block diagram of an example of an information processing device using the present invention. This information processing device includes a CPU10, an I10 interface section IL screen I/F1 for a printer and an FDD, etc.
2, VRAM 13, main memory 14, system bus 1
5.

FIG. 2 is a block diagram of a screen used in this information processing apparatus. This information processing device uses a liquid crystal as its main display device, and is configured to be able to use a CRT at the same time. Screen■/Signal line 2 created by F21
5, an image is displayed on the CRT 22. Furthermore, an image is displayed on the liquid crystal 24 by creating a signal line 26 for driving the liquid crystal using the liquid crystal I/F 23 based on the signal line 25. Signal line 25 that normally drives the CRT
The frequency is matched to the horizontal synchronization frequency of the CRT, so it is a high frequency of 21 MHz. LCD I
/F23 operates asynchronously with signal line 25, so
The liquid crystal can be driven no matter what the frequency of the signal line 25 is.

In a system that projects images on the CRT 22 and liquid crystal 24 at the same time, if the frequency of the signal line 25 is lowered, an image will appear on the liquid crystal 24, but the CRT (cathode ray tube) 2
2, the image does not appear properly.

This is because it does not match the horizontal synchronization frequency of the CRT. Therefore, by switching the frequency of the signal line 25, the frequency of the signal line 250 can be lowered when displaying only the liquid crystal.

In the information processing device shown in Figure 1, the part that consumes the most power is the VRAM connected to screen 1/F12.
It is 13. Furthermore, the screen I/F 12 must always operate in order to display the screen even when the information processing apparatus is powered on and the CPU 1O is not performing any processing.

By the way, DPRAM used in VRAM13
, SRAM SDRAM, etc. - When the operating frequency becomes higher, the power consumption increases. In other words, in order to reduce the power consumption of information processing equipment, VRAM1
Lowering the operating frequency in step 3 will be most effective.

In order to lower the operating frequency of the VRAM 13, the CLK frequency applied to the screen 1/F12 shown in FIG. 1 may be lowered. Therefore, as an example, FIG. 3 shows a circuit example in which the frequency of CLK is halved.

The CLK input to CLK IN31 is CLKCHG.
When the signal 33 is "L", it is output as is to CLKOUT 32, and when CLKCHG33 is "H", the frequency is divided and the period is halved.

Flip-flop 35.36 and N0R34 are CLK
This is a circuit that determines the timing for switching the frequency. C
Sending a signal to the LKCHG33 may be done by software, or may be done by a hardware switch.

As mentioned above, the circuit shown in Figure 3 allows the first
By lowering the CLK applied to the screen I/F 12 in the figure, the power consumption of the information processing device can be easily lowered.

Particularly in the case of a battery-powered information processing device, by changing the CLK applied to the screen 1/F depending on the CRT, liquid crystal, or other display, the battery life can be extended without reducing the performance of the main body.

[Effects of the Invention] In an information processing device, current consumption can be easily and significantly reduced by lowering the clock frequency of at least the circuit section that controls the display device. In particular, in the case of an information processing device using a battery or the like as a power source, the usage time can be significantly extended.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of an information processing device used in the present invention. FIG. 2 is a block diagram of a screen used in the information processing apparatus according to the present invention. FIG. 3 is a diagram showing an example of a circuit for halving the frequency of CLK according to the present invention. 10: CPU 11: Printer, FDD etc. 12° screen I/F 13: VRAM 14: Memory 22: CR7 display tube 23: Liquid crystal I/F 24 Liquid crystal 31: Clock input 32, clock output

Claims (1)

[Claims] Arithmetic processing unit, main storage device, memory control unit, display control unit,
An information processing device comprising at least a display device and an external storage device, characterized in that the information processing device includes a mechanism for switching a clock signal of a circuit unit that controls the display device of the information processing device in order to reduce power consumption. .