JPH0367331A - Microprocessor - Google Patents

Abstract

PURPOSE:To decrease the number of microinstructions by sharing a common microinstruction when a macro instruction includes a microinstruction which is common to another macro instruction. CONSTITUTION:A microentry address generating means decodes a macroinstruction an produces a proper macroentry address which entries a microinstruction proper macroentry address which entries a microinstruction poper to the macroinstruction. When the macroinstruction corresponds to some other macroinstructions, a common microentry address is produced for entry of the common microinstruction. Thus a common microinstruction can be shared by some macroinstructions if the common microinstruction is previously stored in a prescribed position of a muROM. As a result, the scale of the muROM is reduced without storing the same microinstruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor, and particularly to a microprocessor that executes macro instructions using micro instructions, and relates to a micro processor intended to reduce the number of micro instructions.

In general, many microprocessors incorporate some of their basic functions in the form of microprograms (by rewriting the microprograms, the architecture can be changed).
It is possible to flexibly respond to the above changes. Firmware written as a microprogram is designed to execute one basic function using a collection of several microinstructions, and in this specification, machine instructions executed by a collection of several microinstructions are referred to as macroinstructions. That's what it means.

[Conventional technology]

Conventional microprocessors include, for example, μ microprocessors that store a large number of microinstructions within the microprocessor.
It is equipped with a ROM (micro ROM), decodes a given instruction, generates an entry address for the corresponding macro instruction, accesses the μROM using this entry address, and executes the macro instruction by executing the micro instruction. There is something. The entry address (netast address) of the next microinstruction to be executed is written in the microinstruction stored in the pROM.
By accessing one microinstruction, several other microinstructions can be sequentially read and one macroinstruction can be executed.

For example, when one macro instruction consists of four micro instructions (a) to (d), first, (a) is accessed by the entry address from the decoder, and then,
By the netast address written in (b), (b)
is accessed, then (c) is accessed by the netast address written in (b), and finally (d) is accessed to complete the execution of one macro instruction.

[Problem to be solved by the invention]

However, in such conventional microprocessors, the first microinstruction is accessed by the microentry address from the decoder, and the microinstructions following this microinstruction in the next or lower order are accessed by μR.
Since this was configured to be executed using the netast address written in the OM, the microinstruction for realizing each macroinstruction was dedicated to that macroinstruction, and even if there was a common microinstruction for each macroinstruction, this It was not possible to share microinstructions.

Therefore, for example, if n microinstructions are common to m macroinstructions, it is necessary to store nX(m-1) additional identical microinstructions.
There was a problem in that the scale of the μROM increased accordingly.

[Purpose of the invention]

Therefore, an object of the present invention is to enable the microinstructions common to each macroinstruction to be shared by each macroinstruction, thereby reducing the number of microinstructions in the μROM.

[Means to solve the problem]

FIG. 1 is a principle block diagram of a microprocessor according to the present invention.

In FIG. 1, a microprocessor is a microprocessor that executes one macro instruction using a plurality of micro instructions. , generates a unique micro-entry address for entering a micro-instruction specific to the macro-instruction, and also generates a common micro-entry address for entering the common micro-instruction when the macro-instruction corresponds to the several macro-instructions. It is configured to include micro entry address generation means.

[Effect]

In the present invention, when one macro instruction is decoded, a micro entry address unique to that macro instruction is generated, and if the macro instruction is a specific instruction that includes a common micro instruction with other macro instructions, generates a common microentry address for accessing the common microinstruction.

Therefore, by storing the above-mentioned common microinstructions in a predetermined location in the μROM, these common microinstructions can be shared by several macroinstructions, and the size of the μROM can be reduced without storing the same microinstructions. can be reduced.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

2 to 8 are diagrams showing an embodiment of the microprocessor according to the present invention, and are examples in which the microprocessor is applied to a microprocessor that performs pipeline control.

First, the configuration will be explained. In FIG. 2, the microprocessor includes an instruction queue 1, a decoder 2, a pipeline control section 3, and a microprogram storage section (for example, μRO
M) an instruction control unit 5 including 4; an instruction execution unit 9 including an address generation unit 6, a register file 7, and an arithmetic unit 8;
A memory control unit 12 including an instruction access control unit 10 and an operand access control unit 11, and a bus control unit 16 including a bus block access monitoring control unit 13, an address monitoring control unit 14, and a data transmission/reception unit 15,
The specific configuration of the decoder 2, which is the key point of the present invention, is as follows:
It is shown in FIG.

The decoder 2 has a function as a micro-entry address generation means, and its configuration includes a first instruction decoder 1 section 17 that decodes the first operation code OP of the instruction (macro instruction) taken out from the instruction queue 1; 2 opcode O
A second instruction decode unit 18 decodes P2, an addressing decode unit 19 including a next stage return request decode unit that decodes the addressing field and indicates the next stage regarding the stage indicating the decode position of the macro instruction, and an extension unit B. It is provided with decoding sections 17 to 20 such as an additional mode decoding section 20 for decoding, and input side latches 21 to 26 and output side latches 27 to 30 that control input/output timing of these decoding sections 17 to 20. , input side lunches 21 to 26 are input from the decoding sequencer 31).

Similarly, the output side launches 27 to 30 operate according to the stage signal φ from the decode sequencer 31. Further, 32 is a selector that selects the decoding result of the first instruction decoding section 17 or the decoding result of the second instruction decoding section 18 and outputs the first entry address to the microprogram storage section 4, and 33 is a second entry address generation circuit. , 34 is an end determination circuit, and the second entry address detection circuit 33 receives an instruction tag (TAG) outputted from the second instruction decoding section 18, for example, as shown in FIG.
Addressing information (ADR3) from the addressing decode unit 19 and size information (31) in the instruction code
2B), and the second command specific to each instruction, for example, shown in FIG.
Generate entry address. The end determination circuit 34 monitors the end instruction signal generated upon the end of reading out a series of microinstructions in the microprogram storage section 4, and
When the end instruction signal is asserted, the selector 32 and the second entry address generation circuit 33 are operated to output the second entry address or the first entry address of the next instruction to the microprogram storage section 4.

Here, the format of the instruction taken out from instruction queue 1 is that the instruction code has a basic length of 16 bits (half word: HW), up to three basic parts, and extensions that are added according to the mode specified by the basic part. The extension is in immediate, displacement or addition mode.

FIG. 7 is a diagram specifically showing the command format, which is divided into a -ship format shown in FIGS. 7(a) to (C) and an abbreviated form shown in FIGS. 7(d) to D). In addition, in the figure, OP, 0P110P2 are the opcode part, S is the operand size specification part, A is the operand specification part, B is the extension part, R is the register specification part, ■ is the immediate value (immediate part), and D is the displacement part. ing. FIG. 7(a) shows a variable length instruction of l operand (first operand part 0PI) type, and the extension part B has a variable length of 16 bits xn (n is an integer including O). FIG. 7(b) shows a variable length instruction with two operands (first operand OP1 and second operand 0P2), and similarly, extension part B has a variable length of 16 bytes×n. FIG. 7C shows an extended operand type variable length instruction, which includes an match part I and a displacement part.

7(d) and 7(e) are variable-length instructions between memory and registers, and FIG. 7(r) is an instruction between registers (for example, 16-bit fixed length).

Figure 4 is a code table specifically showing some instructions including common micro instructions.
It is related to. The instruction types shown in Figure 4 are, in particular,
Microinstructions for several cycles executed immediately after startup are common instructions with other instructions. In this embodiment, when these instruction types are decoded by each instruction decoding section 17 to 20, 2
One entry address is generated. That is, when the instruction is decoded by the decoding units 17 to 20 and the instruction is any (macro) instruction shown in FIG. 4, the first instruction decoded according to FIG.
After outputting an entry address and executing the common microinstruction specified by this address, it outputs a second entry address and executes a microinstruction specific to that (macro)instruction.

FIG. 8 is a diagram showing the operation of the microprocessor of this embodiment. In FIG. 8, DC is the decoding stage, A
C is an address calculation stage, Ml is a micro read stage, OB is an operation stage, and OW is a result write stage, and each stage is pipeline processed.

The processing is performed as follows. First, the DC fetches instructions from instruction queue 1 into each decoder (a), (b),
TAG and ADR of the decoding results of each decoder in AC
3 etc. to the second entry address detection circuit 33 (c) (d), and outputs the first entry address as a result of decoding by MIIO to the address bus 35 (e). As a result, the common microinstruction in the microprogram storage section 4 is entered and transferred to the instruction execution section 9. and,
The netast address is read out from the microprogram storage section 4 onto the address bus 35, and the next common microinstruction is read out from the microprogram storage section 4 in accordance with this next address. When reading of all common microinstructions is completed, a termination instruction (h) is asserted. When the instruction shown in FIG. 4 is executed according to this assertion, Mr20 transfers the second entry address from the second entry address control circuit 33 to the address bus 35.
Based on this second entry address, a microinstruction specific to the current instruction (instruction decoded by DC) is read from the microprogram storage unit 4 and transferred to the instruction execution unit 9. Thereafter, the unique microinstruction is transferred to the instruction execution unit 9 according to the netast address from the microprogram storage unit 4 and executed.

As described above, in this embodiment, when one (macro) instruction is decoded by the DC and the instruction is any of the instructions shown in FIG. 1 entry address) is generated, and then, as the common microinstruction ends, an entry address (second entry address) unique to that (macro) instruction is generated.
Among the large number of microinstructions stored in the microinstruction unit 4, microinstructions that are common to some macroinstructions can be shared by each macroinstruction, and therefore, the same microinstructions are stored in the microprogram storage unit 4 in duplicate. This is no longer necessary, and the number of microinstructions in the microprogram storage section 4 can be reduced.

〔Effect of the invention〕

According to the present invention, the microinstructions common to each macroinstruction can be shared by each macroinstruction, and the number of microinstructions in the μROM can be reduced.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Figs. 2 to 8 are diagrams showing an embodiment of the microprocessor sensor according to the present invention, Fig. 2 is an overall configuration diagram thereof, and Fig. 3 is a decoder thereof. Figure 4 is a diagram showing the common instructions for several cycles immediately after startup, Figure 5 is a diagram showing the decoding format for the first entry address, and Figure 6 is the second entry. FIG. 7 is a diagram showing the address, FIG. 7 is a diagram showing the instruction form, and FIG. 8 is a timing chart explaining the processing operation. 2... Decoder (micro entry address generation means). Figure 6 shows the second entry address

Claims (1)

[Claims] A microprocessor that executes one macro instruction using a plurality of micro instructions, wherein some of the macro instructions include the same common micro instructions. A micro-entry address that generates a unique micro-entry address for entering a micro-instruction specific to an instruction, and also generates a common micro-entry address for entering the common micro-instruction when the macro instruction corresponds to the several macro instructions. A microprocessor characterized by comprising generating means.