JPH0367348B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly relates to a structure of a capacitor section of a MIS type semiconductor memory device and a method of manufacturing the same.

The most widely used memory device today that uses insulated gate field effect transistors is the so-called "one-transistor type" memory device, which consists of a single transistor and a capacitor placed adjacent to it. It is. In this memory device, the gate of the transistor is connected to the word line, one of the source and drain diffusion layers is connected to the digit line, and the presence or absence of a significant charge accumulated under the capacitor gate corresponds to inversion information.

In recent years, as the integration of semiconductor devices has progressed, there has been a demand for miniaturization of elements. When miniaturizing a one-transistor type memory device, a decrease in capacitance value must be avoided as much as possible in order to maintain ease of information determination and resistance to radiation. Therefore, in the conventional technology,
The decrease in C _S has been suppressed by reducing the thickness of the insulating film, but this method is not always sufficient because of the increase in pinhole density and the decrease in breakdown voltage due to thinning of the film. Nakatsuta.

In recent years, in order to increase the capacitance value, a method has been devised in which the capacitance value is increased by forming a groove in the semiconductor substrate of the capacitor part to increase the surface area of the capacitor. However, the above method has a drawback in that leakage current tends to flow between the grooves when the groove spacing between adjacent memory cells, that is, one-transistor type memory elements is shortened. The reason for this is that the depletion layers extending from the side surfaces of the grooves into the substrate coalesce, resulting in pantesthrough between the grooves, and as a result, current flows between the grooves. As a result, the electricity stored in the cell disappears and information is lost. One possible way to prevent the above phenomenon is to use a substrate with a high impurity concentration, but this is not preferable because it affects device characteristics other than the capacitive portion.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above drawbacks, provide a structure in which the distance between adjacent grooves can be narrowed, and a high capacitance value can be obtained.

Another object of the present invention is to provide an effective method that eliminates the above drawbacks and prevents punch-through even when the distance between adjacent grooves is shortened.

In the present invention, impurities of the same conductivity type as the substrate and impurities of the opposite conductivity type are diffused on the sides of the groove, and the diffusion depth of the impurity of the conductivity type opposite to that of the substrate is made shallower than the diffusion depth of the impurity of the same conductivity type as the substrate. This structure is based on the novel idea that punch-through can be suppressed and a high capacitance value can be obtained by utilizing the capacitance of the PN junction formed on the side surface.

That is, a feature of the present invention is that a groove is selectively formed on the surface of a semiconductor substrate, and a first impurity having the same conductivity type as the semiconductor substrate and having a higher concentration than the semiconductor substrate is formed in the groove from the surface of the sidewall toward the inside of the sidewall. and a second impurity region of opposite conductivity type, the depth of the first impurity region from the sidewall surface is greater than the depth from the sidewall surface of the second impurity region,
An insulating film is provided on the surface of the portion of the semiconductor substrate that includes the groove, and an electrode is provided on this insulating film, whereby 1.
The present invention relates to a semiconductor device in which a capacitive portion of a transistor type memory element is formed.

Other features of the present invention include the steps of ion-implanting impurities of the same conductivity type as the substrate into the semiconductor substrate, diffusing the impurities into the substrate by heat treatment, for example, and increasing the depth of the impurities into the substrate. The method of manufacturing a semiconductor device includes the steps of forming a groove shallower than the depth to which the impurity is diffused, and forming an insulating film and a capacitor electrode on the substrate surface in a region including the groove.

Next, embodiments will be described based on the drawings.

1 to 8 show a first embodiment.

In FIG. 1, a thick field oxide film 2 is selectively formed on a p-type silicon substrate 1 by a conventional selective oxidation method. The silicon substrate is exposed in areas other than the field area. Next, as shown in FIG. 2, an oxide film 3 is deposited on the entire surface by vapor phase growth, and openings are selectively formed in the oxide film 3 by a photo-etching process using a photoresist 4. Grooves are formed in the substrate by an etching process. Ordinary reactive ion etching is used for etching, and oxide film 3 is used together with photoresist 4 as an etching mask. Next, as shown in FIG. 3, the oxide film 3 and photoresist 4 are removed. Next, as shown in FIG. 4, an oxide film 5 doped with a p-type impurity is deposited over the entire surface, and a photo-etching process is performed to remove the oxide film 5 from areas other than the area where the capacitor portion is to be formed. Next, a heat treatment is performed to diffuse p-type impurities from the oxide film into the substrate, thereby obtaining a p-type high concentration region 6. The high concentration region 6 suppresses the spread of the depletion layer from the groove side surface into the substrate, and prevents punch-through between adjacent structures. Next, as shown in FIG. 5, by the same process as in FIG.
Dope type impurities. The resulting diffusion depth of the n-type impurity region 8 is made sufficiently shallower than that of the p-type impurity 6. This step lowers the threshold voltage of the capacitor, and a sufficient amount of charge storage can be obtained.

Next, as shown in FIG.
is removed, a thin capacitor insulating film and gate oxide film 9 are formed on the exposed surface, and a polycrystalline silicon layer 10, for example, is formed thereon, and this is selectively removed to form a capacitor electrode 10' and a gate electrode. 10" (Fig. 7). Next, a surface CVD silicon dioxide film 12 is formed.
Form a surface protective film such as
The metal wiring layer 13, which becomes a word line, is connected to the extended gate electrode 10'' (FIG. 8).

In FIG. 9, capacitor sections having grooves formed as in the first embodiment are provided on the left and right sides of the central field insulating film 2, and a voltage is applied to the capacitor electrode 10'. The voltage V _G was varied to measure the leakage current flowing between the left and right capacitance sections as indicated by the thick arrows ←→, that is, the leakage current between adjacent cells. The results are shown in FIG. This shows that the P ⁺ high concentration region 8 of the present invention reduces the leakage current between cells.

Next, a second embodiment of the present invention will be explained with reference to FIGS. 11 to 16.

In FIG. 11, a thick field oxide film 22 is selectively formed on a p-type silicon substrate 21 by an ordinary selective oxidation method. Next, p-type impurities such as boron 23 are ion-implanted. The energy of implanted ions is from several tens of KeV to several hundred KeV, and the amount of implantation is
Approximately 10 ¹² to 10 ¹³ /cm ² is appropriate. Next, as shown in FIG. 12, a p-type impurity is diffused into the substrate by heat treatment to form a heavily doped p ⁺ -type region 14. The appropriate heat treatment temperature is 1000 to 1200°C and the time is several hours to several tens of hours. Thus, the depth of the diffusion layer 14 is several microns.
It will be about. Next, as shown in FIG. 13, grooves are formed by a photoetching process using photoresist 15. The depth of the groove is set to such an extent that it does not exceed the depth of the diffusion layer 4. As shown in FIG. 14, a gate insulating film and a capacitor insulating film 16 are formed, and then a conductive film, for example polycrystalline silicon 17, which is to become a capacitor and a gate electrode is deposited. Next, as shown in FIG. 15, the polycrystalline silicon is removed by a photoetching process except for the portions that will become the capacitor electrode 17' and the gate electrode 17''.Next, as shown in FIG. Using polycrystalline silicon as a mask, an n-type impurity n is introduced by ion implantation into the source and drain regions 18 of the transistor.One of the source and drain regions of the transistor is connected to the bit line, and the other is connected to the capacitor of the memory cell. Next, the entire surface is covered with an insulating film 19, and contact openings are formed by a photo-etching process.
Next, electrode metal 20 is deposited and word lines are formed through a photo-etching process, and memory cells are completed on the left and right sides of the central field insulating film 12, respectively.

[Brief explanation of drawings]

1 to 8 are cross-sectional views showing a first embodiment of the present invention. FIG. 9 is a sectional view of a test device made to confirm the effects of the first embodiment, and FIG. 10 is a diagram showing the above effects based on experimental data. 11 to 16 are cross-sectional views showing a second embodiment of the present invention. In the figure, 1, 21... p-type silicon substrate, 2, 22... field oxide film, 3... vapor phase growth oxide film, 4, 15... photoresist, 5...
...Oxide film doped with p-type impurity, 6,14...
p-type impurity diffusion layer, 7... oxide film doped with n-type impurity, 8... n-type impurity diffusion layer, 9, 16...
...gate oxide film, capacitor insulating film, 10, 17...polycrystalline silicon film, 10', 17'...capacitor electrode, 1
0'', 17''... Gate electrode, 11... N-type source and drain region, 12, 19... Interlayer insulating layer,
13, 20... Wiring layer that becomes a word line, 23...
It is a boron ion.

Claims (1)

[Claims] 1. In a semiconductor device having a one-transistor storage element configured by one transistor and a capacitor provided adjacent to the transistor in a semiconductor substrate, a first impurity having the same conductivity type as the substrate is contained in the semiconductor substrate. A region is selectively provided, a groove is selectively provided in the surface of the semiconductor substrate where the capacitance is to be formed, the depth of the groove is made shallower than the depth of the first impurity region, and the groove is made shallower than the depth of the first impurity region. A second layer of conductivity type opposite to that of the substrate is provided on the surface of the semiconductor substrate at the bottom and sidewalls of the substrate.
an impurity region is provided, and the depth of the second impurity region from the semiconductor substrate surface at the bottom and sidewall portions of the trench is made shallower than the depth of the first impurity region, and the surface of the semiconductor substrate including the trench is An insulating film is provided on the insulating film, and an electrode is provided on the insulating film, thereby forming the capacitance of a one-transistor type memory element.