JPH036734A - Instruction fetching system - Google Patents

Abstract

PURPOSE:To maintain the fetching effect of instructions and to improve the processing ability of an instruction fetching system by preparing an instruction fetching part to store the instructions in accordance with the action patterns. CONSTITUTION:An instruction executing part 400 knows a program to be executed hereafter and the type of the action pattern of the program based on the hitherto process results and lets an instruction fetching part 200 know the address of an instruction and the type of an action pattern A via a control line 401 and an information line 402 reads the contents of the pattern A out of a memory 100 to store them and simultaneously fetches the instruction. Then the part 200 checks the operand of the instruction and stores this instruction in a queue 300 as long as the next fetching address of the instruction does not change. Thus it is possible to prefetch an address that is never changed from the next fetching address based on the due action pattern and to improve the processing ability of an instruction fetching system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an instruction fetch method, and particularly to an instruction fetch method for prefetching instructions by an information processing processor operating under program control.

[Conventional technology]

Conventionally, in this type of instruction fetch method, an instruction fetch section sequentially fetches logical instructions at the next address, stores them, and supplies them to an instruction execution section. When the instruction execution unit executes a judgment instruction etc. and changes the address of the next instruction to be executed,
In response to an instruction from the instruction execution section, the instruction fetch section clears the stored instruction group and starts fetching from the specified address.

[Problem to be solved by the invention]

The conventional instruction fetch method described above sequentially fetches the instructions at the next address in a fixed format, so when executing a judgment instruction etc. and moving execution to another address, it is necessary to fetch the instructions from that point. This has the drawback that the effect of preempting instructions is lost, leading to a decrease in processing performance.

In general, in a process that may move execution to another address where a judgment instruction has been executed, the instruction execution unit
For example, in the outgoing process of a telephone exchange, if the process from making a call to receiving a call to a rotary dial and a push button dial is configured in one program, and the process for the rotary dial and the process for the push button dial diverge at the time of a judgment command, the instruction execution unit From the previous process of obtaining the location of the calling phone, etc.
The problem of not being able to take advantage of the above-mentioned effect of preemption is that even though it is known which path to take, that is, whether to move or not, and the form of each branched program is known. have.

[Means to solve the problem]

The instruction fetch method of the present invention stores a series of programs including judgment instructions and an operation pattern specifying whether or not to move execution to another address in the judgment instructions of this program in a processor having an instruction prefetch function. an instruction execution unit that determines the type of operation pattern of the series of programs from the processing up to that point before execution of the series of programs; an instruction fetch unit that reads this operation pattern from the memory and stores the instruction and changes the next fetch address according to this operation pattern when there is a possibility that the execution address of the instruction fetched from the memory will change; It is configured by having a queue that stores instructions from the fetch section and outputs them to the instruction execution section in first-in order.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a memory 100 is a storage device that stores programs, data, and operation patterns, an instruction fetch unit 200 is a control unit that preempts instructions from the memory 100, and a queue 300 is an instruction fetch unit. Part 20
a register that sequentially stores instructions fetched by 0;
The instruction execution section 400 is a section that sequentially reads and executes instructions from the queue 300. Also, the control line 401 and the information line 4
02 is an information line through which the instruction execution unit 400 notifies the instruction fetch unit 200 of the address and type of operation pattern of the program to be executed subsequently based on the processing results up to that point.

FIGS. 2 and 3 show an example of a program for explaining the operation shown in FIG. 1, and two operation patterns A and B used for fetching this program, respectively.
It shows the contents of. The operation of FIG. 1 will be explained below with reference to FIGS. 2 and 3.
From the processing results up to that point, 00 knows, for example, the program shown in FIG. 2 to be executed next and the operation pattern A, which is the type of operation pattern of that program. Therefore, the instruction execution unit 400 notifies the instruction fetch unit 200 of the address of the instruction 1 and the type of operation pattern A via the control unit 401 and the information line 402. The instruction fetch unit 200 reads and stores the contents of the operation pattern A from the memory 100, and also fetches the instruction 1. Next, the instruction fetch unit 200 examines the operand of the instruction 1, and determines whether the instruction 1 is the next instruction such as a judgment instruction or a jump instruction. Knowing that the fetch address does not change, instruction 1 is placed in the queue 300.
At the 0th order, the instruction fetch unit 200 checks instruction 2 and, since this instruction is a judgment instruction, checks the already stored operation pattern A. "1" indicates whether to branch to the layer where the judgment instruction appears or to select the next address.

Since the first bit of operation pattern A is "1", the instruction fetch unit 200 fetches instruction 6 using the branch address indicated in instruction 2. Note that at this time, instruction 2 does not need to be stored in the queue 300, and since the fetched instruction 6 is not an instruction that changes the address to be fetched next, it is stored in the queue 300 as it is.Next, instruction 7 is fetched, but this instruction does not change the address Since there is a possibility that the command will change, operation pattern A is checked again, and since the second bit is "0", instruction 7 is stored in the queue 300 as is. Note that for an instruction such as instruction 7, the next address is determined after the calculation by the program, and it is unavoidable that the fetch must be re-fetched.
If it is stored in 0, the next instruction 8 will be fetched, but the address of this instruction will not change in the next fetch, so it will be stored in the queue 300.0 If instruction 9 is fetched next, the next fetch address will change. , the operation pattern A is checked and the third bit is "1 pass", so it is not stored in the queue 300 as in the case of instruction 2,
Address instruction 5 specified by instruction 9 is fetched and stored in queue 300. As a result, instruction execution unit 400 executes instructions 1, 6.7, and 8.5 stored in queue 300.

Note that operation pattern B in FIG. 3 is used when the instruction execution unit 400 performs processing in which the address of the next instruction after instruction 2 does not branch in the program in FIG. 2 based on the processing results up to that point.

〔Effect of the invention〕

As described above, the present invention has the effect of being able to prefetch an instruction that will not be changed from the next fetch address according to the operation pattern, and improving processing performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 and FIG.
The figure is a diagram showing an example of a program and an operation pattern for explaining the operation of FIG. 1. 100...Memory, 200...Instruction fetch unit, 3
00...Queue 400...Instruction execution unit.

Claims (1)

[Claims] In a processor having an instruction prefetch function, a memory for storing a series of programs including a judgment instruction and an operation pattern specifying whether or not to move execution to another address in the judgment instructions of this program, and the series of programs. an instruction execution unit that determines the type of operation pattern of this series of programs from the processing up to that point before execution; and upon receiving the type of operation pattern determined by the instruction execution unit, reads this operation pattern from the memory; an instruction fetch section that stores the instruction and changes the next fetch address according to this operation pattern when there is a possibility that the execution address of the instruction fetched from the memory may change; and an instruction fetch section that stores the instruction from the instruction fetch section; An instruction fetch method comprising: a queue that is first output to the instruction execution unit in the order of first input.