JPH0367357B2 - - Google Patents
Info
- Publication number
- JPH0367357B2 JPH0367357B2 JP15091484A JP15091484A JPH0367357B2 JP H0367357 B2 JPH0367357 B2 JP H0367357B2 JP 15091484 A JP15091484 A JP 15091484A JP 15091484 A JP15091484 A JP 15091484A JP H0367357 B2 JPH0367357 B2 JP H0367357B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- thin film
- wiring board
- ground
- multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、大型コンピユータ等の電子機器に使
用して好適な多層配線基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multilayer wiring board suitable for use in electronic equipment such as large-sized computers.
一般に、高速大容量処理が求められる大型コン
ピユータ等の電子機器においては、配線の高密度
化および高速化が同時に要求されている。
Generally, in electronic devices such as large computers that require high-speed, large-capacity processing, higher wiring density and higher speed are required at the same time.
従来、この種の電子機器には、第１図に示すよ
うに接地配線１、電源配線２の導体印刷配線、接
続パツド３およびスルーホール配線４を有し、複
数のセラミツクグリーンシート５を積層してなる
セラミツク積層配線基板６上に、微細な薄膜配線
７，８ヴイアホール配線９を有する絶縁薄膜１
０，１１および部品取付端子１２を有する絶縁薄
膜１３を積層してなる薄膜多層配線部１４が設け
られた多層配線基板が前記の要求を満足させるも
のとして採用されている。ここで、多層配線の層
間絶縁材として誘電率が低い樹脂材料を用いた場
合にはより一層高速化が可能である。なお、同図
において１５は端子ピン接続パツド、１６は端子
ピンである。 Conventionally, this type of electronic equipment has a ground wiring 1, a printed conductor wiring for a power supply wiring 2, a connection pad 3, and a through-hole wiring 4 as shown in FIG. 1, and has a plurality of ceramic green sheets 5 laminated. An insulating thin film 1 having fine thin film wirings 7, 8 and via hole wiring 9 on a ceramic laminated wiring board 6 made of
A multilayer wiring board provided with a thin film multilayer wiring section 14 formed by laminating insulating thin films 13 having terminals 0, 11 and component mounting terminals 12 has been adopted as one that satisfies the above requirements. Here, when a resin material with a low dielectric constant is used as the interlayer insulating material of the multilayer wiring, even higher speeds are possible. In the figure, 15 is a terminal pin connection pad, and 16 is a terminal pin.
ところが、このように構成された多層配線基板
においては、セラミツク積層配線基板６上の薄膜
配線７，８と接地配線１との距離がセラミツクグ
リーンシート５の厚さによつて左右されるため、
薄膜配線７，８の特性インピーダンスはセラミツ
クグリーンシート５の厚さがばらつくと、設計値
に対しばらつくという欠点があつた。また、セラ
ミツク積層配線基板６はセラミツクグリーンシー
トを焼成して形成するため、通常0.1〜0.3mm程度
しか薄くできず、特性インピーダンスをあまり低
くすることができなかつた。この結果、薄膜配線
７，８の特性インピーダンスが所定の値まで下が
らず、これら配線７，８と接続する回路素子（図
示せず）とのインピーダンス不整合があつたり、
クロストーク特性が悪化したりするという欠点が
あつた。 However, in the multilayer wiring board configured as described above, the distance between the thin film wirings 7 and 8 on the ceramic laminated wiring board 6 and the ground wiring 1 depends on the thickness of the ceramic green sheet 5.
There is a drawback that the characteristic impedance of the thin film wirings 7 and 8 varies with respect to the designed value when the thickness of the ceramic green sheet 5 varies. Further, since the ceramic laminated wiring board 6 is formed by firing ceramic green sheets, it can usually be made thinner by only about 0.1 to 0.3 mm, making it impossible to reduce the characteristic impedance very much. As a result, the characteristic impedance of the thin film wirings 7 and 8 does not fall to a predetermined value, resulting in an impedance mismatch between the wirings 7 and 8 and the circuit elements (not shown) connected to them.
The disadvantage was that the crosstalk characteristics deteriorated.
そこで、第２図に示すようにセラミツク積層配
線基板６の表面を研磨し、これに薄膜法により接
地配線網１７を形成して薄膜配線７，８の特性イ
ンピーダンスを調整する多層配線基板もあるが、
セラミツク研磨表面の粗さは通常最小でも0.2μｍ
Ra程度であり、その凹凸により接地配線網１７
形成時のエツチング工程でエツチング残りが生じ
るという不都合があつた。 Therefore, as shown in FIG. 2, there is a multilayer wiring board in which the surface of the ceramic laminated wiring board 6 is polished and a ground wiring network 17 is formed thereon by a thin film method to adjust the characteristic impedance of the thin film wirings 7 and 8. ,
The roughness of polished ceramic surfaces is usually at least 0.2 μm.
The ground wiring network 17
There was a problem in that etching residue was left during the etching process during formation.
本発明はこのような事情に鑑みなされたもの
で、セラミツク積層配線基板と薄膜多層配線部間
に設けた樹脂膜上に薄膜配線の特性インピーダン
スを補正するための薄膜状接地配線パターンを形
成するとともにこの薄膜状接地パターンとセラミ
ツク積層配線基板内の導体印刷配線とを接続する
というきわめて簡単な構成により、精密な接地配
線パターン化ができ、薄膜配線の最適な特性イン
ピーダンス値を設定できる多層配線基板を提供す
るものである。以下、その構成等を図に示す実施
例によつて詳細に説明する。
The present invention has been made in view of the above circumstances, and includes forming a thin film ground wiring pattern on a resin film provided between a ceramic laminated wiring board and a thin film multilayer wiring section for correcting the characteristic impedance of the thin film wiring. The extremely simple configuration of connecting this thin film ground pattern to the printed conductor wiring within the ceramic laminated wiring board allows for precise ground wiring patterns and allows for the creation of a multilayer wiring board that can set the optimal characteristic impedance value of the thin film wiring. This is what we provide. Hereinafter, the configuration and the like will be explained in detail by referring to embodiments shown in the drawings.
第３図は本発明に係る多層配線基板を示す一部
破断斜視図で、同図以下において第１図および第
２図と同一の部材については同一の符号を付し、
詳細な説明は省略する。同図において、符号２１
で示すものはポリイミド系の樹脂膜で、前記セラ
ミツク積層配線基板６の表面を覆うようにこの基
板６と前記絶縁薄膜１０間に形成されている。こ
の樹脂膜２１上には接続パツド２２および前記薄
膜配線７，８の特性インピーダンスを補正するた
めのシート状の薄膜状接地配線パターン２３が形
成されている。この接地配線パターン２３と前記
薄膜配線７，８とによる静電容量によつて薄膜配
線７，８の特性インピーダンスを調整することが
できる。
FIG. 3 is a partially cutaway perspective view showing a multilayer wiring board according to the present invention, and in the following figures, the same members as in FIGS. 1 and 2 are designated by the same reference numerals.
Detailed explanation will be omitted. In the figure, reference numeral 21
1 is a polyimide resin film, which is formed between the ceramic laminated wiring board 6 and the insulating thin film 10 so as to cover the surface of the ceramic laminated wiring board 6. Formed on this resin film 21 are connection pads 22 and a sheet-like thin film ground wiring pattern 23 for correcting the characteristic impedance of the thin film wirings 7 and 8. The characteristic impedance of the thin film wirings 7 and 8 can be adjusted by the capacitance of the ground wiring pattern 23 and the thin film wirings 7 and 8.
このように構成された多層配線基板において
は、接地配線パターン２３が樹脂膜２１上すなわ
ち薄膜多層配線部１４の直下に形成されているた
め、薄膜配線７，８の特性インピーダンスが薄膜
配線７，８自体の寸法と絶縁薄膜１０，１１の膜
厚、材質と接地配線パターン２３の寸法により決
定される。この場合、絶縁薄膜１０，１１の膜厚
は薄膜配線７，８が薄膜法により形成されるた
め、かなり自由に設定することができる。また絶
縁薄膜１０，１１を有機高分子材料で形成する
と、誘電率が３〜７で膜厚が１〜50μｍとなり、
薄膜配線７，８の最適な特性インピーダンス値を
幅広い値の中から決定することができる。 In the multilayer wiring board configured in this manner, the ground wiring pattern 23 is formed on the resin film 21, that is, directly under the thin film multilayer wiring section 14, so that the characteristic impedance of the thin film wirings 7, 8 is lower than that of the thin film wirings 7, 8. It is determined by its dimensions, the thickness and material of the insulating thin films 10 and 11, and the dimensions of the ground wiring pattern 23. In this case, the thickness of the insulating thin films 10 and 11 can be set fairly freely since the thin film wirings 7 and 8 are formed by a thin film method. Furthermore, when the insulating thin films 10 and 11 are formed of an organic polymer material, the dielectric constant is 3 to 7 and the film thickness is 1 to 50 μm.
The optimal characteristic impedance value of the thin film wirings 7 and 8 can be determined from a wide range of values.
また、接地配線パターン２３はポリイミド系樹
脂膜の滑らかな表面上に薄膜法により形成される
ため、パターン形成時のエツチング工程でエツチ
ング残りが無い精密なパターン化が可能となり、
この結果、特性インピーダンスを高精度にコント
ロールすることができる。 Furthermore, since the ground wiring pattern 23 is formed by a thin film method on the smooth surface of the polyimide resin film, it is possible to form a precise pattern with no etching residue during the etching process during pattern formation.
As a result, the characteristic impedance can be controlled with high precision.
なお、本発明は接地配線パターン２３が直流的
に接地されていなくても、交流的に接地されてい
れば同様の特性インピーダンス調整効果を有する
ので、接地配線パターン２３は接地配線１の代わ
りに電源配線２と接続されていても良い。 In addition, in the present invention, even if the ground wiring pattern 23 is not grounded in a direct current manner, if it is grounded in an alternating current manner, it has the same characteristic impedance adjustment effect. It may be connected to wiring 2.
また、本発明は接地配線パターン２３を第４図
に示すように網目状に形成し、２つの配線層の配
線７，８が交差する個所だけ網の線幅を他の部分
より太くしてクロストーク特性を向上させること
ができる。 Further, in the present invention, the ground wiring pattern 23 is formed in a mesh shape as shown in FIG. Talk characteristics can be improved.
以上説明したように本発明によれば、セラミツ
ク積層配線基板と薄膜多層配線部間に樹脂膜を形
成すると共に、この樹脂膜上に薄膜配線の特性イ
ンピーダンスを補正するための薄膜状接地配線パ
ターンを形成し、この薄膜状接地パターンをセラ
ミツク積層配線基板内の導体印刷配線に接続した
ので、従来のようにパターン形成時のエツチング
残りを生じることが無く精密なパターン化が可能
となり、薄膜配線の最適な特性インピーダンス値
を設定することができる。
As explained above, according to the present invention, a resin film is formed between the ceramic laminated wiring board and the thin film multilayer wiring section, and a thin film ground wiring pattern is formed on the resin film to correct the characteristic impedance of the thin film wiring. This thin film ground pattern is connected to the printed conductor wiring inside the ceramic laminated wiring board, making it possible to form precise patterns without leaving etching residue during pattern formation, which is ideal for thin film wiring. A characteristic impedance value can be set.
第１図および第２図は従来の多層配線基板を示
す断面図、第３図は本発明に係る多層配線基板を
示す一部破断斜視図、第４図は他の実施例を示す
平面図である。
１……接地配線、２……電源配線、４……スル
ーホール配線、５……セラミツクグリーンシー
ト、６……セラミツク積層配線基板、７，８……
薄膜配線、１４……薄膜多層配線部、２１……樹
脂膜、２３……接地配線パターン。
1 and 2 are cross-sectional views showing a conventional multilayer wiring board, FIG. 3 is a partially cutaway perspective view showing a multilayer wiring board according to the present invention, and FIG. 4 is a plan view showing another embodiment. be. 1... Ground wiring, 2... Power supply wiring, 4... Through hole wiring, 5... Ceramic green sheet, 6... Ceramic laminated wiring board, 7, 8...
Thin film wiring, 14... Thin film multilayer wiring section, 21... Resin film, 23... Ground wiring pattern.
Claims (1)
印刷配線およびスルーホール配線を有する複数の
セラミツクグリーンシートを積層してなるセラミ
ツク積層配線基板と、このセラミツク積層配線基
板の上部に設けられた薄膜配線を有する薄膜多層
配線部とを備えた多層配線基板において、前記セ
ラミツク積層配線基板と前記薄膜多層配線部間に
樹脂層を形成するとともに、この樹脂層上にシー
ト状もしくは網目状の薄膜状接地配線パターンを
形成し、この薄膜状接地配線パターンと前記導体
印刷配線とを接続したことを特徴とする多層配線
基板。1. A ceramic laminated wiring board formed by laminating a plurality of ceramic green sheets having printed conductor wiring and through-hole wiring consisting of a power wiring layer or a ground wiring layer, and a thin film wiring provided on the top of this ceramic laminated wiring board. In the multilayer wiring board having a thin film multilayer wiring section, a resin layer is formed between the ceramic multilayer wiring board and the thin film multilayer wiring section, and a sheet-like or mesh-like thin film ground wiring pattern is formed on the resin layer. 1. A multilayer wiring board, characterized in that the thin film ground wiring pattern and the printed conductor wiring are connected to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15091484A JPS6130099A (en) | 1984-07-20 | 1984-07-20 | Multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15091484A JPS6130099A (en) | 1984-07-20 | 1984-07-20 | Multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6130099A JPS6130099A (en) | 1986-02-12 |
| JPH0367357B2 true JPH0367357B2 (en) | 1991-10-22 |
Family
ID=15507150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15091484A Granted JPS6130099A (en) | 1984-07-20 | 1984-07-20 | Multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6130099A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2005067359A1 (en) | 2003-12-26 | 2007-07-26 | 株式会社村田製作所 | Ceramic multilayer substrate |
| EP4641629A1 (en) * | 2022-12-23 | 2025-10-29 | Kyocera Corporation | Wiring board, electronic component mounting board using wiring board, and electronic module |
-
1984
- 1984-07-20 JP JP15091484A patent/JPS6130099A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6130099A (en) | 1986-02-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |