JPH0367377B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital synchronization circuit for synchronizing digital signals.

Digital signal synchronization methods include a method that uses a tank circuit to achieve synchronization with an input data signal, and a method that uses an RLL circuit (phase locked loop). Furthermore, there is a method of achieving start-stop synchronization using a signal of a constant period, but all of the above methods have the drawback that synchronization is disturbed by dropouts in data. For this reason, we have filed an application for the following ``clock regeneration method.'' The method extracts the edges of a specific pattern in the signal,
This is a method of achieving synchronization using the edge signal.
As a method for extracting the edges of this specific pattern, the patent application adopts a pattern extraction method in which an input data signal is input to a shift register, and output is performed when the output pattern of each bit of the shift register becomes a predetermined pattern. However, if the input data signal has a very large fluctuation in the time axis, the number of times the pattern is extracted by the pattern extraction method decreases, and synchronization may not be achieved. This problem could be solved by providing a circuit for extracting many kinds of specific patterns, but this would increase the scale of the circuit, so it was necessary to reduce it.

It is an object of the present invention to further improve our application and to provide a data synchronization circuit which improves cases where data synchronization is disturbed due to dropouts and the like, and at the same time improves the performance of following fluctuations in the time axis of input data.

In order to prevent synchronization of an input digital signal by an edge signal at a timing deviated due to a dropout or the like, the present invention provides a circuit for extracting a specific pattern, uses it as a synchronization input of an asynchronous synchronous circuit, and A time gate window is opened within a range that does not adversely affect data discrimination by decoding the synchronization circuit, and the edge signal of the input digital signal is located in the gate window.The edge signal of the input digital signal is located in the gate window.The edge signal of the input digital signal is used together with the specific pattern extraction circuit output, and the start-stop type It is characterized by being used as a synchronous input of a synchronous circuit.

Embodiments illustrating the present invention will be described in detail below. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, in which 1 is an input terminal for an input digital signal, 2 is an edge detection circuit that generates an edge signal 3 of input terminal 1, and 4 is an input terminal. terminal 1
A specific pattern extraction circuit extracts a specific pattern and outputs a pattern extraction signal 5, and 6 outputs an OR output 7 of the pattern extraction signal 5 and an AND circuit 15.
OR circuit; 8 is an oscillator that oscillates at a frequency N times the input digital signal speed; 9 is the output of oscillator 8;
10 is a circuit that divides output 9 by 1/N and outputs OR output 7.
The phase of the discrimination window signal 11 for data discrimination is adjusted by controlling the frequency division ratio. 12 is a decoder circuit that generates the time gate window signal 13; 14;
is an AND circuit which inputs the edge signal 3 and the time gate window signal 13 and outputs 15.

Next, the operation of the embodiment of the present invention will be explained in detail with reference to the timing diagram of FIG.

In the timing diagram of Fig. 2, N=8, T is the normal value for the edge interval, and the specific pattern extraction circuit 4 extracts a pattern of length T, and the broken line is the normal edge for input digital signal 1. This shows an example where an edge is shifted due to noise or the like.

Therefore, the edge signal 3 and pattern extraction signal 5 have a pulse width of T/8 according to the timing shown in the figure.
Although it is possible in principle to widen the pulse width of the time gate window signal 13 to a maximum length of T, it is necessary to narrow it to a range that does not adversely affect data discrimination. In this example, the edge signal 3 is normally expected to be in the T/8 region, which is the center value of the time gate window signal, but since the edge signal 3 is allowed to shift in the +T/8 region on both sides, the time gate Set a pulse width of 3/8T as a window signal and wait for edge signal 3 to be input. Even if a certain width is provided for the time gate window signal in this way, the influence on the data discrimination window signal 11 is slight.

When input data has large fluctuations on the time axis, if only the output of the pattern extraction circuit of the pattern extraction signal 5 is expected, the frequency of output of the pattern extraction signal 5 will decrease and synchronization will be compromised. Therefore, by expanding the time gate window signal 13 to around T/8, which has a slight influence on the data discrimination window signal 11, the edge signal of the input digital signal can also be used as a synchronization input.
The output frequency of OR output 7 does not decrease. In this way, it is possible to cope with cases where the input data has large fluctuations on the time axis.

Next, the edge detection circuit 2 will be explained in detail with reference to the circuit diagram of FIG. Input digital signal 1 to first stage D
The output 20 is input to the second stage D-type flip-flop 21 to obtain an output 22. Both outputs 20 and 22 are input to an exclusive OR circuit 23 to generate an edge signal 3. Reference numeral 16 is a clock input of D-type flip-flops 19 and 21.

Next, the specific pattern extraction circuit 4 will be explained in detail with reference to the circuit diagram of FIG. Input digital signal 1
The input is input to a 10-stage shift register 24, the first stage output 25 and the final stage output 27 are respectively inverted by inverter circuits 28 and 29, and input to an input AND circuit 30.
As input. Further, the eight outputs 26 of the intermediate stage excluding the first stage and the final stage of the shift register 24 are input to the input AND circuit 30 as they are.

As described above, according to the present invention, even when input data has large time axis fluctuations, the edge signal of the input digital signal is located in the time gate window decoded by the asynchronous circuit, and the specific pattern extraction circuit outputs the edge signal. By using this in combination with the synchronization input of the start-stop synchronization circuit, synchronization can be achieved without reducing the frequency of occurrence of the synchronization input. In addition, when the time axis fluctuation of the input data is small, as in this example, the specific pattern is extracted with an accuracy of T/8, and the time gate window that includes T/8 at both ends has only a minor effect on the data discrimination window signal. It is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital synchronous circuit according to the present invention, FIG. 2 is a timing diagram showing the operation of the embodiment, FIG. 3 is a circuit diagram of the edge detection circuit of FIG. 1, and FIG. FIG. 1 is a circuit diagram of the specific pattern extraction circuit shown in FIG. 2; edge detection circuit; 4; specific pattern extraction circuit; 8; oscillator; 10; frequency dividing circuit; 12; decoder.

Claims (1)

[Claims] 1 A pattern extraction circuit that detects a predetermined pulse width determined by the transmission rate of the input digital signal, an oscillation circuit, and an output signal of the oscillation circuit that divides the frequency of the output signal of the pattern extraction circuit. an edge detection circuit for detecting an edge of the digital signal; a decoder circuit to which the output signal of the frequency divider circuit is supplied and generates a time gate window; an AND circuit that takes the AND of the output signal of the edge detection circuit and the output signal of the decoder circuit; and an output of the AND circuit. A digital synchronous circuit comprising: an OR circuit which calculates the logical sum of the signal and the output signal of the pattern extraction circuit, and controls the initial state of the frequency dividing circuit using the logical sum signal.