JPH036740U - - Google Patents
Info
- Publication number
- JPH036740U JPH036740U JP6550589U JP6550589U JPH036740U JP H036740 U JPH036740 U JP H036740U JP 6550589 U JP6550589 U JP 6550589U JP 6550589 U JP6550589 U JP 6550589U JP H036740 U JPH036740 U JP H036740U
- Authority
- JP
- Japan
- Prior art keywords
- bus
- internal bus
- relay device
- lines constituting
- internal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Bus Control (AREA)
Description
第１図は本考案の一実施例の構成ブロツク図、
第２図は偶数信号線、奇数信号線に挿入されてい
る第１、第２の出力ドライバの詳細を示す接続図
、第３図は動作の一例を示すタイムチヤート、第
４図は従来のバス中継装置の一例を示す構成ブロ
ツク図である。
ＢＳ１……上位外部バス、ＢＳ２……下位外部
バス、ＢＳ０……内部バス、ＦＦ１，ＦＦ２……
フリツプフロツプ、ＤＲ１，ＤＲ２……第１、第
２の出力ドライバ。
FIG. 1 is a block diagram of an embodiment of the present invention.
Figure 2 is a connection diagram showing details of the first and second output drivers inserted in the even and odd signal lines, Figure 3 is a time chart showing an example of operation, and Figure 4 is a conventional bus FIG. 2 is a configuration block diagram showing an example of a relay device. BS1... Upper external bus, BS2... Lower external bus, BS0... Internal bus, FF1, FF2...
Flip-flop, DR1, DR2...first and second output drivers.
Claims (1)
するバス中継装置において、 前記内部バスを構成するデータ線のうち半数に
当該内部バスの整定を待たずにデータ伝送を行う
第１の出力ドライバと、 前記内部バスを構成するデータ線のうちの残り
の半数に当該内部バスの整定及び、スタガリング
に必要な所定の時間を待つてデータ伝送を行う第
２の出力ドライバと、 前記第１、第２の出力ドライバの開閉を制御す
る２つの同期式フリツプフロツプと を設けたことを特徴とするバス中継装置。[Scope of Utility Model Registration Claim] In a bus relay device having an internal bus that connects an upper bus and a lower bus, data transmission is performed on half of the data lines constituting the internal bus without waiting for the internal bus to settle. and a second output driver that waits for a predetermined time required for settling and staggering of the internal bus before transmitting data to the remaining half of the data lines constituting the internal bus. A bus relay device comprising: two synchronous flip-flops that control opening and closing of the first and second output drivers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6550589U JPH036740U (en) | 1989-06-05 | 1989-06-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6550589U JPH036740U (en) | 1989-06-05 | 1989-06-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH036740U true JPH036740U (en) | 1991-01-23 |
Family
ID=31597392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6550589U Pending JPH036740U (en) | 1989-06-05 | 1989-06-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH036740U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9976621B2 (en) | 2004-06-17 | 2018-05-22 | Illinois Tool Works Inc. | Pre-deformed thermoplastics spring and method of manufacture |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS539439A (en) * | 1976-07-14 | 1978-01-27 | Hitachi Ltd | Information gate system |
-
1989
- 1989-06-05 JP JP6550589U patent/JPH036740U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS539439A (en) * | 1976-07-14 | 1978-01-27 | Hitachi Ltd | Information gate system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9976621B2 (en) | 2004-06-17 | 2018-05-22 | Illinois Tool Works Inc. | Pre-deformed thermoplastics spring and method of manufacture |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH036740U (en) | ||
| JPS63118659U (en) | ||
| JPS62162754U (en) | ||
| JPH02126434U (en) | ||
| JPH0191955U (en) | ||
| JPS60161894U (en) | alarm clock | |
| JPS62183257U (en) | ||
| JPS5984629U (en) | Data bus transfer mode switching control device | |
| JPS63159441U (en) | ||
| JPS62169851U (en) | ||
| JPS60174902U (en) | Servo device | |
| JPS60170801U (en) | Control system switching device | |
| JPS60167462U (en) | Image processing device | |
| JPS6444475U (en) | ||
| JPS6146623U (en) | keyboard interface device | |
| JPS6035290U (en) | Calendar-clock system bus coupling device | |
| JPH0277747U (en) | ||
| JPS5858602U (en) | Drive output control device | |
| JPS59118380U (en) | Remote monitoring control device | |
| JPS63196136U (en) | ||
| JPS62142601U (en) | ||
| JPS599426U (en) | indicator circuit | |
| JPS5915145U (en) | character display device | |
| JPS63114348U (en) | ||
| JPS61147447U (en) |