JPH0368020A - Digit matching circuit for division operand - Google Patents

Abstract

PURPOSE:To efficiently execute the digit matching processing of an operand of a floating point division by adding some hardware to a floating point adding circuit. CONSTITUTION:When a digit matching mode register 16 is in a regular mode, a result selector 14 always selects an output of an adder 55, and shift counting selectors A 50, B 51 execute all the same operation as a conventional circuit. When the digit matching mode register 16 is in a digit matching mode of a division operand, the result selector 14, the shift counting selector A 50, and the shift counting selector B 51 always output the output of an equalizing shifter A 52, the output of a digit matching shift counting register 17, and '0', respectively. By using this constitution, digit matching is executed by a prescribed sequence, the result of comparison of an absolute value is stored in an indicator register 35 through an absolute value comparator 34, and the result of right shift is stored in a result register 56.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a division operand digit alignment circuit, and in particular to a floating-point operand digit alignment circuit that aligns the digits of the mantissa of the dividend so that its absolute value is smaller than the mantissa of the divisor prior to division of floating-point data. This invention relates to a division operand digit alignment circuit used in a divider.

BACKGROUND TECHNOLOGY Conventionally, in some types of information processing devices (e.g., Japanese Patent Application Laid-Open No. 57-041737 "Dividing Device") that executes division of floating point data by replacing it with the product of a dividend and a divisor, the dividend is calculated before the operation. It is necessary that the following relationship holds between and the divisor.

1 Dividend mantissa 1 + 1 Divisor mantissa I... (1) In such an information processing device, for example, an adder and a shifter for fixed-point data as shown in FIG. 2 are used to calculate the divisor and dividend. Digit alignment processing is performed so that the relationship in equation (1) is not satisfied.

In FIG. 2, operand registers A22 and B25
are registers that store the one inverse of the dividend and divisor, respectively. The sign comparison circuit 27 compares the signs of both operands and supplies the comparison result to the inversion instruction circuit 28.

The inversion instruction circuit 28 instructs the inversion circuit 29 to invert according to the comparison result and the addition/subtraction mode set in the addition/subtraction type register 23.

This inversion circuit 29 inverts the operand data in the operand register B25 in response to the inversion instruction.

Adder '3' adds the output of operand register A22 and the outputs of the two inverting circuits.

The result of this addition is manually input to the Gerd register 33 via the selector 32, and is also input manually to the disconnection/single value comparison circuit 34.

This absolute value comparison circuit 34 is a circuit that compares the magnitude of the absolute value of the dividend and the divisor based on the sign of the operand data of the operand register A22 and the addition output of the adder 31, and the result is stored in the indicator register 35. Ru.

The shifter 30 shifts the mantissa part of the operand data input via the selector 36 to the right to align the digits, and performs the right shift according to the contents of the shift count register 26.

This shift count is generated by a shift count generation section consisting of a leading sign count generation circuit 37, leading sign registers A38 and B39, and a shift count generation circuit, and is supplied to the shift count register 26 via a selector 41. It is.

The digit alignment processing operation for the dividend and divisor will be described below with reference to FIG. It is assumed that the given dividend and divisor are in two's complement format.

(1) Store the mantissa of the dividend in the operand register A22 and the mantissa of the divisor in the operand register B25, and set the addition/subtraction type register 23 to the absolute value comparison type.

(2) The sign comparison circuit 27 compares the signs of the outputs of the operand register A 22 and the operand register B 25, and compares the sign of the output of the sign comparison circuit 27 with the addition/subtraction type register 2.
3 output, the inversion instruction generating circuit 28 determines whether or not the output of the operand register B25 is to be inverted.

(3) When the inversion instruction generation circuit 28 outputs an instruction to invert the output of the operand register B25, the bit pattern of the output of the operand register B25 is inverted in the inversion circuit 27, replaced with a one's complement number, and the adder 31 The carry to the lowest order of the adder 31 is set to "1", and if no inversion instruction is issued, the output of the operand register B25 is output as is from the inversion circuit 27, and the carry to the lowest order of the adder 31 is set to "0". ”, and the adder 31 adds the output of the operand register A22 and the output of the inverter 29.

(4) Based on the sign of the output of the adder 31 and the output of the operand register A22, the absolute value comparison circuit 34 determines whether or not operand register A1-operand register B holds true, and stores the result in the indicator register 35. .

(5) If it is determined from the output of the indicator register 35 that the following relationship has been established: operand register A x 1 operand register B, operand register A22. The mantissa parts of the dividend and divisor given to B25 are used as they are as the mantissa parts of the operand of division. Further, if it is determined that the relationship is as follows: operand register A a1 operand register B, the digit alignment process in (6) and subsequent steps is continued.

(6) The shifter manual selector 36 selects the output of the operand register B25, the leading sign count generation circuit 37 calculates the leading sign count (number of consecutive sign bits) of the output of the operand register B25, and stores it in the leading sign register A38. Next, the thick input selector 36 selects the output of the operand register A22, and the leading sign count generation circuit 37 calculates the leading sign count of the operand register 8 output and stores it in the leading sign register A38.

(7) In the thick count generation circuit 40, a shift count is generated by subtracting the output of the leading sign register A39 from the output of the leading sign register A38, and the result is stored in the shift count register 26.

(8) In the sick 30, the output of the operand register A22 output from the sick human selector 36 is shifted to the right according to the output of the shift count register 26, and the result is stored in the operand register A22 and the result register 33.

(9) Similar to (2), (3), and (4) above, the absolute values of the operand register A 22 output and the operand register B output 25 are compared, and the absolute value comparison circuit 34 output is stored in the indicator register 35.

(lO) If it is determined by the output of the indicator register 35 that the following relationship has been established, the mantissa part of the divisor given in advance to the operand register B25 and the dividend stored in the result register 33 The result of the right shift is used as the mantissa of the division operand. Further, if it is determined that operand register A≧1 operand register B, the following digit alignment process (1■) is executed.

(11) Store the shift force unit for one digit defined by the base number of the exponent in the shift count register 26, and (8
), and the output of the shifter 30 is transferred to the operand register A22 and the result register 33 again.
Store in.

(12) Perform the same absolute value comparison as in (2), (3), and (4) above, and store the result in the indicator register 35.

(13) If it is determined by the indicator output 35 that the relationship of 1 operand A1 x 1 operand B1 has been established, the mantissa part of the divisor given in advance to the operand register B25 is taken and the dividend stored in the Gerd register 33 is shifted to the right. Use the result as the mantissa of the divisor operand. If not, see (11) and (12) above.
, Repeat (13).

Although a description of the processing of the exponent part is omitted in FIG. 2, it goes without saying that each time the mantissa of the dividend is shifted to the right, the exponent value of the dividend must be increased in accordance with the number of shifts.

Let's look at a specific example here. Note that the base of the exponent is 2
(index value n-5-2'').

■Let A be the mantissa part of the dividend. Let B be the mantissa part of the divisor.

A -0,001010...0 B -0,0010...O → A ≧ B ■ Find the leading sign count LSALSB of A and B. →LSA Sanction 3. LSB-3 shift count-L
SA-LSB 3-3 10 ■ Shift A to the right using the shift count (-0) from ■ above to become A1 A 1- A -0,001010...0-4 A1
Mi B ■ Set the shift count to "1" from the base of the exponent, and further shift AI to the right to set it to A2.

A 2-0.00010LO...O B -0,0010......0→lA
2 <IBI ■1A21<A2 from IBI. Let B be the mantissa part of the dividend and the divisor, respectively (the exponent part of the dividend is O according to the number of right shifts).
(used with an increase of +1-1).

The above-mentioned conventional digit alignment circuit for division operands using adders and shifters for fixed-point data repeatedly executes shifts and absolute value comparisons, which has the disadvantage that control is complicated and execution time for digit alignment is long. There is.

However, in an information processing device that executes operations on floating-point data, an adder for floating-point data as shown in FIG. 3 is added independently of the adder and thick for fixed-point data shown in FIG. Many are equipped with equipment.

The adder for floating point data in FIG. 3 operates as follows.

That is, the exponents of operand A and operand B used in the calculation are stored in exponent registers A42, 843, respectively, and the mantissas are stored in mantissa registers A46. Store in B47.

Thereafter, an exponent subtracter A44 subtracts the output of the exponent register A42 from the output of the exponent register 843, and an exponent subtracter B45 subtracts the output of the exponent register B43 from the output of the exponent register A42. Exponent subtractor A, 44
From the output and the sign of the exponent subtractor B45 output, operand A
The equalize shift count of the mantissa part of the operand B is output from the equalize count selector A50, and similarly, the equalize shift count of the mantissa part of the operand B is output from the equalize count selector B51.

Here, when exponent register A≧exponent register B, the output of equalize count selector A50 becomes “0”, and from equalize count selector B51, the value of 1 exponent register A−exponent register B, that is, the value of exponent register B45
Output is printed.

Conversely, in the case of exponent register - exponent register B, equalize count selector A50 outputs the value of I index register A - exponent register B1, that is, the output of exponent subtractor A44, and "0" is output from equalize count selector B51. Output.

In the equalize shifter B53, the mantissa register 46
The output is shifted to the right by the output of the equalize count selector A50, and in the equalize shifter B53, the output of the mantissa register B47 is shifted to the right by the output of the equalize count selector B51.

In the inverter 54, the output of the equalize shifter B53 is inverted to one's complement as necessary, and in this case, the adder 55
A carry is generated at the lowest position.

In the adder 55, the output of the equalization shifter 52 and the output of the inverter 54 are added, and the result is stored in the gel register 56.

Here, if we follow the structure of the floating-point adder in Figure 3, it has a structure that is similar to the fixed-point data adder in Figure 2 with a right-thick called an equalize shifter added.
If the shift count of the equalize shifter can be calculated from a source other than the difference in exponents (for example, from the difference between the leading sign counts of the dividend and the divisor), then the right shift of the dividend and the absolute value in the conventional example explained using FIG. It follows that comparisons can be performed by this floating point adder circuit.

Purpose of the Invention The present invention has been made with attention to the above-mentioned points, and its purpose is to add a small amount of hardware to a floating point addition circuit to perform digit alignment of operands used in division of floating point data. The object of the present invention is to provide a digit alignment circuit for division operands that can be efficiently performed by simply adding .

According to the present invention, there is provided a digit alignment circuit for a division operand in a floating-point divider that aligns the mantissa part of the dividend so that its absolute value is smaller than the mantissa part of the divisor before executing division of floating-point data. Shifting means for shifting the operand data to the right to align the mantissa parts of the operand data according to the difference in the exponent parts of the two operand data to be subjected to arithmetic processing; a floating point addition/subtraction device including addition/subtraction means for adding and subtracting operand data; digit alignment shift count generation means for generating a shift count necessary for digit alignment of the dividend;
Absolute value comparison means for determining whether the absolute value of the output after digit alignment is smaller than the absolute value of the divisor from the sign of the mantissa part of the dividend and the output of the addition/subtraction means; and the floating point addition/subtraction device. A division operand comprising: control means for controlling the shift count generated by the digit alignment shift count generation means to be supplied to the shift means in response to an external command used for digit alignment of the division operand. The digit alignment circuit is obtained.

Example Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit block diagram showing an embodiment of the present invention,
The floating point addition/subtraction circuit shown in FIG. 3 has been added with the division operand digit alignment function shown in FIG. In FIG. 1, parts equivalent to those in FIG. 2.3 are indicated by the same reference numerals.

Figure 1 is almost the same as Figure 3; exponent register A42, exponent register B43, mantissa register A46, mantissa register B.
47, exponent subtractor A44, exponent subtractor B45, equalize shifter A52, equalize shifter B53, sign comparison circuit 48, addition/subtraction type register 57, inversion instruction generation circuit 49, inversion circuit 54, adder 55, result register 5
6, and has all the functions of the normal floating point adder shown in FIG.

In addition, in FIG. 1, there is a mode register called a digit alignment mode register 16, which is a mode that distinguishes whether the adder 55 for floating point data is used for normal addition of floating point data or for digit alignment of a division operand. is set.

That is, when the digit alignment mode register 16 indicates the addition mode of floating point data, the result selector 14 always selects the output of the adder 55.The shift count selector hole 50, the shift count selector B5
1 is the equalize count selector A50 in FIG.
．． It works exactly the same as B51.

In other words, when the sign of the output of the exponent subtractor B45 is negative, that is, (exponent register A42 <exponent register B43), the shift count selector hole 50 outputs the output of the exponent subtractor A44, and the shift count selector B51 outputs "0". If not, shift count selector B
51 outputs the output of the exponent subtracter B45, and the shift count selector hole 50 outputs 0''.

On the other hand, when the digit alignment mode register 16 indicates the digit alignment mode of the division operand, the result selector 1
4 always outputs equalize shift tom 5/2, and shift count selector hole 50 is digit alignment shift count register 1.
7 outputs, and the shift count selector B51 outputs "0".

Note that in FIG. 1, the shift count generation circuit and the like shown in FIG. 2 are omitted.

The digit alignment of the division operand will be explained below using FIG.

(1) Set the digit alignment mode register 16 to the digit alignment mode for the division operand, and set the digit alignment shift count register 17 to "O". Further, the addition/subtraction type register 57 is set to the absolute value comparison type, and the mantissa parts of the dividend and the divisor are stored in the mantissa register A46 and the mantissa register B47, respectively.

(2) In the sign comparison circuit 48, the mantissa register A46,
The signs of the outputs of the B47 are compared, and it is determined whether or not the output of the equalize shifter 853 is to be inverted in the inversion instruction generation circuit 49 based on the output of the sign comparison circuit 48 and the output of the addition/subtraction type register 57.

(3) Equalize shifter A52. At B53, mantissa register A46. The outputs of B47 are shifted to the right according to the outputs of shift count selector holes 50 and 851, respectively. In reality, the mantissa register A 46 output is right-shifted by the digit alignment shift count register 17 output, and the mantissa register B 47 output is not right-shifted.

(4) Equalize shifter 85 from inversion instruction generation circuit 49
When an instruction to invert the 3 output is issued, the inverter 54 inverts the output of the equalize shifter B53 to make it a 1's complement, and the carry to the lowest order of the adder 55 is set to "1".
If there is no inversion instruction, the output of the equalize shifter 853 is output as is from the inverter 54, the carry to the bottom of the adder 55 is set to "Oo," and the adder 55 outputs the output of the equalize shifter A52. and the output of the inverter 54 are added.

(5) From the sign of the output of the adder 55 and the output of the mantissa register A46, the lVi number register A is used in the absolute value comparison circuit 34.
It is determined whether 1 minus 1 mantissa register B1 holds true or not, and the result is stored in indicator register 35.

(6) If it is determined that the relationship of mantissa register A1 x 1 mantissa register Bl is established from the output of the indicator register 35, mantissa register A46 and mantissa register B
The mantissa parts of the dividend and divisor given in step 47 are used as they are as the mantissa parts of the operand of the division, and if not, the processing from (7) onwards is continued.

(7) Store the right shift count of the dividend obtained from the difference between the leading sign counts of the dividend and the divisor, which is the output of the shift count generation circuit 40 shown in FIG.

(8) Simultaneously execute the same dividend right shift and absolute value comparison as in (2), (3), (4), and (5) above, and input the output of the absolute value comparison circuit 34, which is the result of the absolute value comparison. The right shift result of the dividend is stored in the result register 56.

(9) If it is determined from the output of the indicator register 35 that the right shift result of the mantissa register A output is 1 times 1 mantissa register B1, then the mantissa register B4
The mantissa part of the divisor given in advance to 7 and the result register 56
The right shift result of the dividend stored in is used as the mantissa of the division operand, and if not, the following (10
) Continue the following processing.

(10) Store a shift count for one digit defined by the base of the exponent in the digit alignment shift count register 17,
The dividend right shift and absolute value comparison similar to those in (2), (3), (4), and (5) are executed simultaneously, and the result of the absolute value comparison is stored in the indicator register 35, and the result of the right shift of the dividend is stored in the result register. 56.

(l()) If it is determined from the output of the indicator register 35 that the right shift result of the mantissa register A output +<1 mantissa register Bl is established, then the mantissa register B
Gelt register 56 that takes the mantissa part of the divisor given in advance to 47
The right shift result of the dividend stored in is used as the mantissa of the divisor operand. And if not (
10)”.

(Repeat step 1().

Although a description of exponent processing has been omitted here, it is clear that each time the mantissa of the dividend is shifted to the right, the exponent value of the dividend must be increased in accordance with the number of shifts.

Effects of the Invention As described above, the present invention has the effect that digit alignment of operands used in division of floating point data can be efficiently performed by simply adding a small amount of hardware to the floating point addition circuit in the shell. be.

[Brief explanation of drawings]

Fig. 1 is a circuit block diagram of an embodiment of the present invention, Fig. 2 is a circuit block diagram of a conventional division operand digit alignment circuit, and Fig. 3 is a circuit block diagram of a generally widely used floating-point addition circuit. It is a diagram. Explanation of symbols of main parts 16... Digit alignment mode register 17...
・Digit alignment shift count register 20...Absolute value comparison circuit 42.43...Exponent register 46.47...Mantissa register 48...Sign comparison circuit 49 ...Reversal instruction circuit 50.51...Shift count selector 52.
53...Sick 54...Inverting circuit 55...Adder

Claims (1)

[Claims] (1) A division operand digit alignment circuit in a floating-point divider that aligns the mantissa of the dividend so that the absolute value is smaller than the mantissa of the divisor before executing division of floating-point data, and performs arithmetic processing. Shifting means for shifting the operand data to the right to align the mantissa parts of the operand data according to the difference in the exponent parts of the two target operand data; and addition/subtraction for adding and subtracting the two operand data after the digit alignment. a floating-point addition/subtraction device including means, a digit-alignment shift count generation means for generating a shift count necessary for digit alignment of the dividend, and a digit-alignment shift count generation means for generating a shift count necessary for digit alignment of the dividend; absolute value comparison means for determining whether the absolute value of the output is smaller than the absolute value of the divisor; and generating the digit alignment shift count in response to an external command for using the floating point addition/subtraction device to align the digits of the division operand. and control means for controlling supply of the shift count generated by the means to the shifting means.