JPH0368036A - Multiprocessor diagnostic system - Google Patents

Abstract

PURPOSE:To realize an overloaded state to a control processor and to execute sufficient diagnosis by impressing a diagnosis load from all the control processors in an auxiliary mode to a diagnostic object control processor. CONSTITUTION:Each central control unit 22 and analyzes transmitted transfer D, and when it recognizes the data as a mode changeover instruction which indicates the changeover from the auxiliary mode to a diagnostic load generation mode, it activates a mode changeover part 221, and after changing the setting of each 1-system control processor and O-system control processor from the auxiliary mode to the diagnostic load generation mode, activates a diagnostic load generation part 222. The diagnostic load generation part extracts a data 231 for diagnosis which is preliminarily stored at a main storage device 23, and transmits this to a common bus 4-1 at a fixed cycle. As a result, the maximum load is impressed to the diagnostic object control processor.

Description

[Detailed Description of the Invention] (Summary) Regarding a multiprocessor diagnostic method for diagnosing a control processor in an overload state, it is possible to apply the maximum overload expected in the multiprocessor system to the control processor to be diagnosed. For this purpose, each processor is duplicated with the maintenance processor, with one being
In a multiprocessor system in which a plurality of control processors, each of which is used as a standby, are connected via a common bus, a maintenance processor switches the operating mode of each control processor that is being used as a standby from a standby mode to a diagnostic load generation mode. A mode switching instruction means is provided for transmitting a mode switching instruction to each control processor being used as a backup via a common bus, and when a mode switching instruction is transmitted to each control processor from a maintenance processor while being used as a backup. , mode switching means for switching the operation mode of the self-control processor from the standby mode to the diagnostic load generation mode; The diagnostic load generating means is configured to provide a diagnostic load generating means for transmitting information from the maintenance processor to a designated control processor via the bus.

[Industrial application field]

The present invention relates to a multiprocessor system, and more particularly to a multiprocessor diagnostic method for diagnosing a control processor in an overloaded state.

For example, in an information processing system such as a switchboard that requires high reliability, a plurality of control processors provided for the purpose of function distribution or load distribution are duplicated, and one is operated as the current use.2. A multiprocessor system is used that is kept on standby as the other standby.

[Conventional technology]

FIG. 5 is a diagram showing an example of a conventional multiprocessor system, and FIG. 6 is a diagram showing an example of a conventional control processor.

In FIG. 5, the multiprocessor system includes - sets of maintenance processors 1 and n x 2 sets of control processors 2, each of which is duplicated (individual control processors are O-system control processors 2.-0 to 270 and 1-system control processors). Processors 2.-1 to 271) are connected by a common bus 4.

Each of the control processors 2 has a configuration as shown in FIG. 6, and one of the duplexed control processors (for example, O-system control processors 2.-0 to 2.-0) accommodates the communication line 3 in the active mode. The control processors 2.=1 to 2.-1 are in charge of transmitting and receiving information, and the other control processors (for example, 1-system control processors 2.=1 to 2.-1) are put on standby in a standby mode.

The maintenance processor 1 also sets the operation mode of each control processor 2, monitors the operation of each control processor 2,
Diagnosis and the like of the disease control processor 2 are executed.

Furthermore, it is assumed that the common bus is also duplicated into 4-0 and 4-1.

In FIGS. 5 and 6, each O-system control processor 2
-0 is set to the active mode and connected to the common bus 4-0, and each 1-system control processor 2-1 is set to the standby mode and connected to the common bus 4-1.
When the system control processor 20 is affected, the maintenance processor 1
is duplicated with the affected control processor 2R-〇, changes the setting of the 1-system control processor 2□-1, which is set to the backup mode, to the active mode, and connects the communication line 3 accommodated in the 0-system control processor 2-0. 1 system control processor 2.1-1
In addition to switching the connection to the common bus 4-0, the fault control processor 2. - Change the setting of 〇 from the active mode to the standby mode, and switch the connection to the common bus 4-1.

Thereafter, the maintenance processor 1 executes diagnosis by transmitting and receiving various data to and from the affected control processor 27-0 via the common bus 4-1.
Diagnosis of the transfer control circuit 21, etc. that transmits and receives various data transferred via the common bus 4-1 from the maintenance processor 1 is relatively easy. When diagnosing the device 22 etc., for example, all other O-system control processors 2. -〇～27--
From 〇 to diagnostic symmetrical control processor 2. There may be cases where it is necessary to perform diagnosis under an overload condition such as transferring bus transfer information to -0 and -0 all at once, but the maintenance processor l itself has at most the same diagnostic load as the control processor 2 of group -0. The diagnostic target control processor 2. It is not possible to apply -0.

[Problem to be solved by the invention]

As is clear from the above explanation, in conventional multiprocessor systems, the maintenance processor independently executed the diagnosis of the affected control processor 27-O. It was impossible to apply the maximum overload expected to the processor system.

An object of the present invention is to make it possible to apply the maximum overload expected in the multiprocessor system to a control processor to be diagnosed.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 1 is a maintenance processor, 2 is a control processor, and 4 is a common bus.

The control processor 2 is duplicated, one for current use and the other for backup.

Reference numeral 100 denotes mode switching instruction means provided in the maintenance processor 1 according to the present invention.

201 is mode switching means provided in each control processor 2 according to the present invention.

Reference numeral 202 denotes diagnostic load generation means provided in each control processor 2 according to the present invention.

[Effect]

The mode switching instruction means 100 sends a mode switching instruction to switch the operation mode of each control processor 2 currently in use as a backup from the backup mode to the diagnostic load generation mode via the common bus 4 to each control processor 2 currently in use as a backup. to communicate.

When the mode switching means 201 receives a mode switching instruction from the maintenance processor 1 while being used as a backup, the mode switching means 201 switches the operation mode of the self-control processor 2 from the backup mode to the diagnostic load generation mode.

The diagnostic load generating means 202 generates a diagnostic load when the mode switching means 201 switches the operation mode of the self-control processor 2 to the diagnostic load generation mode, and generates a diagnostic load to a control processor designated by the maintenance processor 1 via the common bus 4. 2.

Therefore, all the control processors in standby mode can apply diagnostic loads to the control processor to be diagnosed, so an overload state corresponding to the maximum load applied to a set of control processors in the multiprocessor system occurs. can be realized, sufficient diagnosis can be performed on the control processor, and the reliability of the multiprocessor system is improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a multiprocessor system according to an embodiment of the invention, FIG. 3 is a diagram showing a control processor according to an embodiment of the invention, and FIG. 4 is a diagram showing an example of bus transfer information. It is a diagram. Note that the same reference numerals indicate the same objects throughout the figures.

2 and 3, a mode switching instruction section 11 is provided in the maintenance processor 1 as the mode switching instruction section 100 in FIG. 1, and a mode switching section 221 is provided as the mode switching section 201 in FIG. A diagnostic load generating section 222 is provided in each control processor 2 as the diagnostic load generating means 202 in FIG.

In FIGS. 2 to 4, each O system control processor 2I
-0 to 2-+ O and 1 system control processor 2, -
1 is set to the active mode and connected to the common bus 4-0, and each of the 1-system control processors 21-1 to 2. . 2
．． .

In the process of executing the diagnosis of 0, the control processor 2 to be diagnosed
Suppose that it becomes necessary to apply an overload to 7-O.

In such a case, the maintenance processor 1
1 and all I-system control processors 21-l to 2,1.1 connected to the common bus 4-1 as the destination address DA. -i and the diagnostic target control processor 27-0, including a global address common to the control processor 27-0, and instructing switching from the backup mode to the diagnostic load generation mode as transfer data D;
In addition, it creates bus transfer information including a mode switching instruction specifying the 1-system control processor 27-0 as a load application target and further adds an end code EM, and sends it to the common bus 4-1.

Each of the 1-system control processors 21-1 to 2□, -1 connected to the common bus 4-1 and the O-system control processor 27
-O, each transfer control circuit 21 analyzes the destination address DA of the bus transfer information transferred from the maintenance processor 1 via the common bus 4-1, and if it recognizes it as a global address, transfers the transfer data D to the internal bus 25. The information is transmitted to each central control device 22 via.

Each central control device 22 analyzes the transmitted transfer data D, and when recognizing it as a mode switching instruction to instruct switching from the standby mode to the diagnostic load generation mode, activates the mode switching unit 221 and controls the respective 1-system control processor 22. -1 to 2,1-
After changing the settings of the +1 and O-system control processor 27-O from the standby mode to the diagnostic load generation mode, the diagnostic load generation section 222 is activated.

The diagnostic load generation unit 222 extracts the diagnostic data 231 stored in the main storage device 23 in advance, and sets the address of the O-system control processor 27-O specified by the mode switching instruction from the maintenance processor I as the destination address DA. , uses the diagnostic data 231 as transfer data D, creates bus transfer information with an end code EM added, and sends it to the common bus 4-1 via the transfer control circuit 21 at a predetermined cycle.

Note that the diagnostic load generation unit 1 provided in the maintenance processor 1
2 similarly creates bus transfer information with the address of the control processor 2-0 to be diagnosed as the destination address DA, the diagnostic data 231 as the transfer data D, and the termination code EM, and transfers the bus transfer information to the transfer control circuit 21 at a predetermined period. common bus 4 via
-1.

As a result, the control processor to be diagnosed 2. - In 〇, all 1-system control processors 2. -1 to 2I%-4-1, the maintenance processor 1, and the self-O system control processor 27-O transfer bus transfer information including all the diagnostic data 231 generated at a predetermined cycle to the common bus 4-1. The maximum overload expected on the multiprocessor system will be applied.

During this time, each O system control processor 21-0 to 2-+ O and 1 system control processor 2. -l is not connected to the common bus 4-1, so it does not receive the bus transfer information sent from the maintenance processor 1, and continues to maintain the current mode.

When the diagnosis target control processor 27-0 is to end the diagnosis in the overload state, the maintenance processor 1 starts the mode switching instruction section 11, includes the global address as the destination address DA, and sends the diagnosis load generation as the transfer data D. Bus transfer information including a mode switching instruction for instructing switching from the mode to the standby mode and further appended with an end code EM is created and sent to the common bus 4-1.

In each of the 1-system control processors 2t1 to 2-+1 and the O-system control processor 27-O connected to the common bus 4-1, each transfer control circuit 21 is connected to the maintenance processor 1 via the common bus 4-1. When the destination address DA of the bus transfer information transferred is analyzed and recognized as a global address, the transfer data D is transmitted to each central control bag R22 via the internal bus 25.

Each central control device 22 analyzes the transmitted transfer data D, and if it recognizes it as a mode switching instruction to instruct switching from the diagnostic load generation mode to the backup mode, the diagnostic load generation unit 222
After stopping the mode switching unit 221, each
System control processors 2-1 to 2. , -1 and the O-system control processor 27-O are changed from the diagnostic load generation mode to the standby mode.

As described above, each 1-system control processor 2.1 connected to the common bus 4-1. -1 to 2-+ 1 and the O-system control processor 2fi-0 return to the standby mode again.

As is clear from the above description, according to this embodiment, all the 1-system control processors 2.1 connected to the common bus 4-1.
-1 to 2-+ 1 and O system control processor 2.
l-0 and the maintenance processor 1 simultaneously transmit the diagnostic data 231 to the diagnostic target control processor 2. , -0, it is possible to realize the maximum overload condition assumed in the multiprocessor system, and the control processor 2. , -〇 can be fully diagnosed.

Note that FIGS. 2 to 4 are only one embodiment of the present invention, and for example, the mode switching unit 201 and the diagnostic load generating unit 202 are the illustrated mode switching unit 221, the diagnostic load generating unit 222, and the diagnostic load generating unit 202. The present invention is not limited to the data 231, and many other modifications may be considered, but the effects of the present invention remain the same in any case. It goes without saying that the multiprocessor system to which the present invention is applied is not limited to that shown in the drawings.

〔Effect of the invention〕

As described above, according to the present invention, in the multiprocessor system, all the control processors in the standby mode can apply the diagnostic load to the control processor to be diagnosed. An overload condition corresponding to the maximum load applied to the control processor can be realized, sufficient diagnostics can be performed on the control processor, and the reliability of the multiprocessor system is improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the invention, FIG. 2 is a diagram showing a multiprocessor system according to an embodiment of the invention, FIG. 3 is a diagram illustrating a control processor according to an embodiment of the invention, and FIG. 5 is a diagram showing an example of bus transfer information, FIG. 5 is a diagram showing an example of a conventional multiprocessor system, and FIG. 6 is a diagram showing an example of a conventional control processor. In the figure, 1 is a maintenance processor, 2 is a control processor, 3 is a communication line, 4 is a common bus, 11 is a mode switching instruction section, 12 is a diagnostic load generation section, 21 is a transfer control circuit, 22
2 is a central control unit, 23 is a main storage device, 24 is a line control device, 25 is an internal bus, 100 is a mode switching instruction means, 2
01 is a mode switching means, 202 is a diagnostic load generating means, 2
Reference numeral 21 indicates a mode switching section, and 222 indicates a diagnostic load generation section. J Main project θ month's mII construction') Processor diagram Nogusu transfer inertia root diagram

Claims (1)

[Claims] In a multiprocessor system in which a maintenance processor (1) and a plurality of control processors (2), each of which is duplicated, one of which is used for active use and the other used as a backup, are connected via a common bus (4). , a mode switching instruction is sent to the maintenance processor (1) to switch the operation mode of each control processor (2) being used as a backup from the backup mode to the diagnostic load generation mode via the common bus (4). A mode switching instruction means (100) is provided for transmitting the mode switching instruction to each control processor (2) in use as a backup, and the mode switching instruction is transmitted to each control processor (2) from the maintenance processor (1) while in use as a backup. mode switching means (201) for switching the operating mode of the self-control processor (2) from the standby mode to the diagnostic load generation mode when the mode is transmitted; generating a diagnostic load and transmitting the diagnostic load from the maintenance processor (1) to a designated control processor (2) via the common bus (4) when switching the diagnostic load generation mode to the diagnostic load generation mode; 1. A multiprocessor diagnostic method, comprising: means (202).