JPH0368048A - Memory test system - Google Patents

Abstract

PURPOSE:To improve speed for processing when a fault is detected by writing the all 0 or 1 of an instruction word, which is defined as one operation instruction, into a memory, applying an error check bit, successively reading out the instruction from the memory and raising a flag in a register at the time of error detection. CONSTITUTION:The all 0 or all 1 of the operation cord of the instruction word is judged as one operation instruction by a decoder 14. Then, the all 0 or 1 is written through a data register 101 to the memory 11 to be tested and simulta neously, the check bit of an error correction code is written into a check bit part. The data of the address of the memory 11 are read out and the data of the address are checked by the check bit in an error correction code detector 12. Next, when the error is detected, the detector 12 suppress the clock of an instruction buffer 13 in a gate 17 and an arithmetic unit 15 raises the flag in the prescribed register 151 and finishes the processing.

Description

[Detailed Description of the Invention] [(Already needed) With regard to fault testing of local memory or control storage in a microprocessor, the purpose is to perform the test at high speed and reduce the amount of hardware, and to all 0 or all 1
is defined as a NOP (no operation) instruction,
All 0s or 1s are written in the operation code section of the data stored in the memory, and an error check bit is added to the operation code section.The instructions written in the memory are sequentially read out, and the error check bits are used to detect errors. When detected, a flag is set in a specified register,
If no error is detected, the configuration is such that the instruction is executed.

(Industrial Application Field) The present invention relates to failure detection in control storage, local storage, etc. built into a microprocessor (MPU).

[Prior Art] A microprocessor (MPU) has a built-in control storage for recording microprograms and firmware, and a local storage.

Therefore, using the MPU, 1. Detecting whether there is a failure in the control storage or local storage in a device that performs some processing is an MP
This is important in today's world where U is used in many industrial areas.

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 4 is a block diagram of an embodiment of the present invention.
FIG. 3 is a flowchart diagram explaining the operation of FIG. 2;

11 is the memory in the MPU that is tested for failures, and 13 is the instruction buffer (hereinafter referred to as IBF).
), 14 is a decoder (hereinafter abbreviated as DEC), 1
5 is an arithmetic unit that performs arithmetic operations in accordance with instructions read from memory. Register 151 is used to set a flag when an error is detected. 19 is an address register that holds a read destination address and a write destination address; 18 is a +1 circuit; and 101 is a data register that holds write data.

The decoder 14 has an operation code of all O or
When all 1s are present, it is determined to be a NOP command.

The above configuration is located within the microprocessor.

A memory 110 stores write data for testing the memory 11. 130 is a register that holds data read from the memory 110, and 140 is an expected value circuit, which functions similarly to the decoder 14.

The operation will be explained below with reference to the drawings.

Step 1 (Flowchart in Figure 4) First, a host device (not shown) checks the memory.
CK program is activated.

Step 2 Next, all addresses of the memory 11 are set in advance.
Write the test data recorded in 0.

Step 3 Set an initial value (first address) in the address register 19 and read the data at the address.

The data is read to rBF13. In parallel, similar data is read out from the memory 110 as well.

The data read from the rBF 13 is decoded by the decoder 14 and input to the arithmetic unit 15. or,
The data read from the memory 110 is sent to the expected value circuit 14.
It is decoded by 0, and this is also manually input to the arithmetic unit 15 (step 6).

Step 5 The two manually input data are compared by the arithmetic unit 15.

Step 8 If they do not match, a flag is set in register 151.

Step 7 When a match occurs, if the address is not the final address, Step 4 The above-described processing is executed regarding the data at the next address.

[Problem to be solved by the invention]

That is, conventionally, predetermined data is written from a memory other than the memory to be diagnosed, the data is read from the memory to be diagnosed, and the data is compared with an expected value to determine whether or not there is an error in the memory.

However, with the above-mentioned means, there is a need for memory other than the memory to be diagnosed, and processing by a host device (or other device) is required. 'A calculation unit requires a comparison function. That is, the amount of hardware becomes relatively large.

Furthermore, since an external device is involved, the processing inevitably becomes slower. Therefore, an object of the present invention is to provide an error detection device that solves all of these problems, has a high processing speed, and requires a small amount of hardware.

[Means for Solving the Problems] In order to achieve the above object, the present invention defines all 0s or all 1s of the operation code of the instruction word as an N0P (no operation) instruction, and the data stored in the memory. All O or 1 in the operation code part of
At the same time, an error check bit is added and written, and the instructions written to the memory are read out sequentially. When an error is detected by the error check bit, a flag is set in a predetermined register and the error is detected. If not detected, the configuration is such that a NOP instruction is executed.

(Operation) Write all O or all 1 to the memory, and then
Executes a NOP instruction (all 0s or all 1s are defined as a NOP instruction).

A check pit detects a fault in the data read by the NOP command.

That is, since no special data is written to the memory and microinstructions are used, failure detection processing can be performed quickly and easily.

〔Example〕

Fig. i is a block diagram of an embodiment of the present invention, and Fig. 3 is a block diagram of an embodiment of the present invention.
FIG. 2 is a flow chart diagram explaining the operation of FIG. 1;

11 is a memory to be tested for faults; 12 is a well-known error correction code detector (ECC circuit);
13 is an instruction buffer (hereinafter abbreviated as rBF), 14 is a decoder (hereinafter abbreviated as DEC), and 15 is an arithmetic unit, which performs arithmetic operations in accordance with instructions read from the memory. There is a register 151 inside the arithmetic unit. One is the read destination address,
18 is a +1 circuit, and 101 is a data register that holds write data.

The decoder 14 has an operation code of all O or
When it is all, it is judged as a NOP command.

The operation will be explained below with reference to the drawings.

Step 1 (Flowchart in FIG. 3) First, test data is written to all addresses in the memory 11. Here, all O's are written through the data register 101. At this time, the check pit section of the memory 11 contains a check pit (C
B) is written at the same time.

Step 2: Set the initial value (first address) in the address register 19 and read the data at the address.

Step 3: In the ECC circuit 12, the CB checks whether or not there is a 3-bit difference in the data at the address.

Step 4 Assume that there are no errors in step 3. The data is sent to the decoder 14 and determined to be a NOP command.

Step 5 If the address is not the final address, Step 8 the arithmetic unit 15 calculates the next address (+
The address added by 1 by 1 circuit is set to address register 1.
Set to 9.

Steps 2 to 5 and 8 described above are repeated unless an error is detected in step 3.

Step 9 If there are no errors up to the final address, the process ends.

Also, a case where an error is detected in step 3 will be explained.

When an error is detected, the ECC circuit 12 outputs 5BE (single bit error signal) or MSB (multi-bit error signal). Said signal passes through gate 16 and the clock of IBF 13 is inhibited by gate 17. If an error is detected, the arithmetic unit 15 sets a flag in a predetermined register 151 and ends the process (
Step 7). The reason for inhibiting the clock of the rBF 13 is to prevent instruction malfunctions.

The case where all 0s are written to the memory has been described above.

By executing the above process, the "'0" of the memory 11 becomes
It is possible to detect cases where the value changes to “1”.

Next, all 1's are written in the memory 11 and the operation shown in FIG. 3 is executed. By executing the above operation, it is possible to detect a case where the ``1'' in the memory 11 turns into ``0''.

The present invention has been described above according to examples.

〔effect〕

By using the NOP instruction, memory errors are detected, that is, microinstructions are directly executed, resulting in faster processing time. In addition, unlike the conventional process of writing data to memory and comparing the written data with the read data, a comparator is not required, so the amount of hardware can be reduced and the complexity can be reduced. Since the test does not use numerical numbers, it has the advantage of being able to easily and clearly detect the location of the failure.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a conventional example, FIG. 3 is an explanation of the operation of the embodiment, Example 1, and FIG. 4 is an explanatory diagram of the operation of the conventional example. ...Memory...ECC...IBF...DEC...Arithmetic unit drilling example 070-+Y-to Part 3

Claims (1)

[Claims] All 0s or all 1s in the operation code of the instruction word
is defined as a NOP (no operation) instruction, writes all 0s or 1s to the operation code section of the data stored in the memory, and writes with an error check bit attached, and the instruction written in the memory is A memory test method characterized in that the instructions are sequentially read, and when an error is detected by the error check bit, a flag is set in a predetermined register, and when no error is detected, the corresponding instruction is executed.