JPH0368069A - Main storage control system - Google Patents

Abstract

PURPOSE:To reduce the number of elements as the controlled system of each indicator by combining first indicators indicating the sequentiality of elements and second indicators indicating the sequentiality of first indicators to perform the sequence control of elements outputted from a vector processor. CONSTITUTION:The request outputted from each vector processor 121 is sent to a storage controller 131. This controller 131 controls the element sequence corresponding to the request by first and second indicators 141 and 151. Plural first indicators 141 indicate the sequentiality of requests inputted to the storage controller 131, and second indicators 151 indicate the sequentiality of first indicators 141. Consequently, first and second indicators 141 and 151 are combined to perform the sequence control of the whole of elements as the sequence controlled system of first indicators 141.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples Effects of the Invention [Summary] Multiple main memories Regarding a main memory control method that performs parallel access to multiple elements, the objective is to provide a main memory control method that facilitates control and is expandable. at least one vector processing device that connects a plurality of elements as a processing unit and outputs a request corresponding to each element;
In the main memory control method, the storage control device controls the order of accesses to the main memory based on the requests output from the vector processing device. a first indicator; and at least one second indicator indicating mutual ordering of the plurality of first indicators;
The configuration is such that the directives are combined to control the order of elements output from the vector processing device.

[Industrial application field]

The present invention relates to a main memory control system that allows parallel access of multiple elements to multiple main memory devices.

[Conventional technology]

In general, in a Vibeline vector computer, speeding up is achieved by increasing the number of pipelines, that is, by increasing the number of elements that can perform operations simultaneously.

In addition, the more interleave you have in the main memory, the more parallel memory access becomes possible.
It is possible to increase the speed.

In memory access control, priority control is necessary to check the memory usage status and to avoid conflicts with accesses to the same bank or accesses with other access devices such as scalar units or channels (I10 processing unit). be.

FIG. 5 shows the configuration of a computer system that processes multiple elements (for example, four elements) in parallel. In the figure, 511 is a vector unit, 521 is a storage control unit (MCU), and 531 and 533 are main storage units (MSU).
are shown respectively.

The vector unit 511 has a vector address generator that generates addresses necessary for accessing the main storage devices 531 and 533, a vector register that stores vector data to be input/output, etc., and has four elements that are processed in parallel. It is possible to output four corresponding requests at the same time.

The storage control device 521 has a priority control section, and these four
Priority control is performed for each request to access the corresponding main storage device.

Each of the main storage devices 531 and 533 is interleaved into a plurality of banks, and each main storage device is connected to the storage control device 521 by a plurality of sets of bus lines. Therefore,
In response to requests output from the vector unit 511, it is possible to simultaneously access four elements in parallel.

By the way, the priority control unit in the storage control device 521 described above determines access conflicts for each bank of the main storage devices 531 and 533, and performs order control to ensure the order of elements. In particular, in the case of random access such as indirect access, the access destination is arbitrarily specified, so accesses between elements that are processed in parallel may conflict, and order control is required.

The priority control unit in the storage control device 521 has a pointer for guaranteeing the order of elements, and by sending requests to each bank of the main storage device 531, 533 while referring to this pointer, the order is guaranteed. control is in place.

FIG. 6 shows an overview of order control in the storage control device 521. In FIG. 5A, A, B, and CD indicate input ports, and requests input from the vector unit 511 are taken into each manual port. When a request is set to each input port, contention control is performed for the set requests. Therefore, a request whose element order can be guaranteed is set to the corresponding input port, and a request whose element order cannot be guaranteed is suspended from being set to the corresponding input port.

Pointer P indicates the priority of each input port with respect to the set of requests by pointing to any of the input ports A-D.

In addition, in the same figure ('b), cycles O to 3 correspond to the operation cycle of sequential control in the storage control device 521, and each number from "O" to "10j" corresponding to the input boats A and -D is Indicates the element number.

Also, "○" indicates a state in which a request has been accepted (set) to the corresponding input port, and "×" indicates a state in which acceptance of a request to the corresponding input port is pending (the access destination is (conflicting states).

Each of input boats A-D has element numbers 4n,
It is assumed that 4n+1.4n+2.4n+3 (n=01...) requests are input, and the control operation in each cycle will be described below.

(2) Cycle O: First, requests with element numbers "0" to "3" are input and set to each of the four input boats A to D. As a result of contention control for each request, if access is permitted for the requests with element numbers "0" and "2", the pointer P points to the input boat A.

This pointer P indicates the input port that can accept the request with the highest priority, that is, the request with the largest element number. Therefore, element number r4. which will be input next to input port A. The request with the element number "6" is the request with the largest element number, and acceptance of the request with the element number "6" that is input next to the input port C is deferred.

(1) Cycle 1: Next, while referring to pointer P, a request is set for each person's support. Since pointer P points to input port A in cycle 0, a request with element number "4" is set in input port A.

As a result of contention control for requests set to each input port, when access is permitted for requests with element numbers "1" and "4", pointer P is updated to point to input port B.

■Cycle 2: Since pointer P points to input boat B, a request with element number "5" is set to this human-powered boat B. In addition, since the input boat C is also ready to accept requests, the pointer P is updated.
A request with element number "6" is taken into input boat C.

Input boat A can accept the request for element number "8", but it is in a suspended state.

As a result of contention control for requests taken into each input port, element number r3. ．． When access is granted for the requests "r5" and "6J," the pointer P is updated to point to the input boat D.

[Problem to be solved by the invention]

As a method of increasing the processing capacity of such a computer system, that is, the number of elements to be processed in parallel, the vector unit 511. There is a method of creating a multiprocessor configuration including a plurality of storage control devices 521 and the like. Processing power is 4
By providing two vector units 511 of element/τ (τ is 1 machine cycle), 8 elements/τ
computer system can be realized. Therefore, by using the common vector unit 511, it is possible to construct various computer systems with different processing capabilities, and benefits such as cost reduction due to sharing of devices can be enjoyed.

Claims (1)

[Claims] (1) At least one main storage device (111), at least one vector processing device (121) that uses one or more elements as a processing unit and outputs a request corresponding to each element, and this vector processing device ( 1
21), wherein the storage control device (131) controls the order of access to the main storage device (111) based on requests output from the main storage device (111). comprising: a plurality of first indicators (141) that indicate the order of elements; and at least one second indicator (151) that indicates the order of the plural first indicators (141); A main memory control method characterized in that a first indicator (141) and a second indicator (151) are combined to control the order of elements output from the vector processing device (121).