JPH0368213A - timing generation circuit - Google Patents

Abstract

PURPOSE:To obtain a timing generating circuit which takes a parameter input of a small number of bits and has a small circuit scale by providing an auxiliary operation execution period signal generating circuit started with a main counted value and a circuit which generates a main operation execution period signal by the output of a main counter circuit. CONSTITUTION:A synchronizing signal A connects a NOR circuit 52 and a NOT circuit 54 of an auxiliary operation execution period signal generating circuit 5. When the synchronizing signal A goes to the high level, the Q output of a JKFF 51, namely a gate signal H indicating the auxiliary operation execution period is initialized to the low level. When a carry signal G of a 4-bit counter 41 of an auxiliary counter circuit 4 first goes to the high level after the synchronizing signal A goes to the high level, the gate signal H indicating the auxiliary operation execution period is changed to the high level. When the carry signal G goes to the high level again then, this gate signal H is returned to the low level. Differences of operation start and end times between the main operation and the auxiliary operation are varied by a third parameter.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is performed periodically on a signal that serves as a reference for an operation, and there are a plurality of operations that take the same amount of time, and these operations are performed as a reference for the operation. This invention relates to a timing generation circuit for a device that differs only in the time at which it starts an operation based on a signal.

[Conventional technology]

FIG. 3 shows the configuration of a conventional timing generation circuit. In this conventional example, the times at which the main operation and the sub-operation are started from the synchronization signal are each expressed by 10-bit parameters, and the time to execute the main operation and the time to execute the sub-operation are equal, and the time is also 10 bits. Assume that it is expressed as a bit parameter. Therefore, the parameters that set the time to start the main operation from the synchronization signal are Plo, Pt+
......, Pl, (Plo is the least significant bit and P1%
The parameter that sets the time to start the sub-operation from the synchronization signal is named the fourth parameter, P4゜, P4□, ......, P4? (P4
゜ is the least significant bit and P4. is the most significant bit), and the parameter that sets the time to execute the main operation and sub operation is P2.
゜, P2. , ..., P29 (P2. is the least significant bit and P2q is the most significant bit).

In FIG. 3, l is a main counter circuit, 3 is a main operation execution period signal generation circuit, 1' is a sub counter circuit, and 3' is a sub operation execution period signal generation circuit. ' have the same configuration, and the main operation execution period signal generation circuit 3 and the sub operation execution period signal generation circuit 3' have the same configuration. Therefore, the main counter circuit 1 and the main operation execution period signal generation circuit 3 will be described here. The sub counter circuit 1' will be explained by adding a dash (') to the reference numeral in the description of the main counter circuit 1 and rereading the "first parameter" as the "fourth parameter." Similarly, regarding the sub-operation execution period signal generation circuit 3', in the explanation of the main operation execution period signal generation circuit 3, a dash (') is added to the symbol and "main operation" is replaced with "sub-operation".
This can be explained by rereading.

The main counter circuit 1 has a 1()-bit selector 11 that switches and outputs the first parameter and the second parameter.
, a 10-bit counter 12 that uses the output of this selector 11 as a load value, a NOR gate 13 for generating a control signal for the selector 11, and a NOR gate for generating a load control signal for the counter 12]4. , NANDA for generating the enable control signal of the counter 12
- and 15.

The main operation execution period signal generation circuit 3 is configured so that the synchronization signal A is “Ho”.
The signal IQ (
A flip-flop (hereinafter abbreviated as JKFF) 31 is connected to J-, which outputs (positive logic) and IQ (negative logic), and signals 2Q (positive logic) and 2Q (negative logic) that indicate the time to execute the main operation.
a NOR gate 33 connected to the terminal of JKFF31, a NOR gate 34 connected to the J terminal of JKFF32, a NAND gate 35 connected to the NOR gate 34, and a terminal of JKFF32. and NOR gate 34
6, a NAND gate 37 connected to the NAND gate 36, a NOT gate 38 that inverts the carry signal C of the 10-bit counter 12 and inputs it to the NOR gate 33, and a NAND gate 38 that inverts the synchronization signal A and inputs it to the NOR gate 33. NOT gate 39 which inputs to gate 36.

Next, the operation will be explained.

FIG. 4 shows the operation of the conventional example shown in FIG.

First, the operation of the main counter circuit 1 will be described.

When the synchronization signal A is input to the NOR gates 13 and 14 in FIG. is initially counted. NA
Since 1Q and 2Q are input to the NDA-to 15, the counter 12 continues counting from the time when the synchronizing signal A becomes "H11" until the execution of the main operation is completed. After being loaded with the value corresponding to the parameter, the counter 12, which continues counting, then puts the carry signal C in the "H++" state. The carry signal C is input to the NOR gate (14) and loads the counter 12 again, but at that time the selector 11 inputs the IQ
is input, an inverted version of the second parameter is output to the counter 12. Then, after being loaded with the value corresponding to the second parameter, the counter 12
continues counting and sets the carry signal C to "H" again to end the counting.

Next, the operation of the main operation execution period signal generation circuit 3 will be described.

jKF using the ゛°H゛° state of the synchronization signal A as the initialization signal.
F31. (7) Input to the J terminal, NOR gate 33, and NOT gate 39, and when the synchronizing signal A becomes IHl" state, 1Q becomes "H" state and 2Q becomes "L" state. Counter 12 The carry signal C of NANDA-to 35
37 and NOT gate 3, 1Q is connected to NANI) gate 35, and 2Q is connected to NAND gate 37, so that IQ is in the "H" state and 2Q is in the "L I+" state. When the carry signal C changes to the ")4" state below, IQ changes to the "L" state and 2Q changes to the "H11" state.

Then, when the carry signal C goes into the "°H°" state, the 1Q continues in the "L°" state and the 2Q changes to the "'L1" state due to an operation of 0 or more. The gate signal will be as shown below.

As is clear from the above explanation, by setting the first parameter and the fourth parameter to different values, the time to start the main operation and the time to start the sub-operation are different,
The time to perform the main operation and the time to perform the sub-operation can be made equal.

In addition, A, B, C, D and A', B'C' in Fig. 3,
D' is A, B, C, D and A'B', C' in Figure 4.
Each corresponds to D'. Further, T in FIG. 3 represents a clock, and R represents a recent signal.

[Problem to be solved by the invention]

Since the conventional timing generation circuit is configured as described above, it is necessary to input parameters with a large number of bits, and there is a problem that the circuit size of counters and the like for sub-operations becomes large.

This invention was made in order to solve the above-mentioned problems, and the purpose is to obtain a timing generation circuit that can perform the same functions as conventional ones with a small number of parameter inputs and a small circuit scale. shall be.

[Means to solve the problem]

The timing generation circuit according to the present invention includes a main counter circuit, a decoding circuit that decodes the count value of the main counter circuit, a sub-counter circuit that inputs the output of the decoding circuit as a start signal, and a sub-operation based on the output of the sub-counter circuit. a sub-operation execution period signal generation circuit that outputs a gate signal indicating a period in which the main operation is executed; and a main operation execution period signal generation circuit that outputs a gate signal indicating the period in which the main operation is executed based on the output of the main counter circuit. It is prepared.

[Operation] In the present invention, the main counter circuit starts the main operation by inputting a parameter corresponding to the time when the main operation is started and a parameter corresponding to the time when the main operation is executed from the synchronization signal. By outputting a signal indicating the time and operation end time to the main operation execution period signal generation circuit, the main operation execution period signal generation circuit outputs a gate signal indicating the period during which the main operation is executed, and also outputs a gate signal indicating the period in which the main operation is executed. A signal representing the state is output to the decoding circuit.

The sub-counter circuit calculates the operation start time and operation end time of the sub-operation by inputting parameters corresponding to the difference between the main operation start time and the sub-operation start time and the output from the decoding circuit. By outputting a signal indicating to the sub-operation execution period signal generation circuit, the sub-operation execution period signal generation circuit outputs a gate signal indicating the period in which the sub-operation is being executed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a tying generation circuit according to an embodiment of the present invention. In this embodiment, the time to start the main operation from the synchronization signal and the time to execute the main operation are each expressed by 10-bit parameters, and the time to start the sub-operation is 4 bits higher than the time to start the main operation. It is assumed that the amount changes by the amount expressed by the parameter. Therefore,
Pl is the parameter that sets the time to start the main operation from the synchronization signal. , Pli, . ,・
..., P2. (P2° is the least significant bit and P2. is the most significant bit), and the third parameter that sets the difference in operation start time between the main operation and the sub operation is P3o, P3
．． , P3z , P33 (P2O is the least significant bit and P
31 is the most significant bit).

In FIG. 1, 1 is a main counter circuit, 2 is a decoding circuit, 3 is a main operation execution period signal generation circuit, 4 is a sub counter circuit, and 5 is a sub operation execution period signal generation circuit.

The main counter circuit 1 includes a 10-bit selector 11 that switches and outputs a first parameter and a second parameter, a 10-bit counter 12 that uses the output of this selector 11 as a load value, and generates a control signal for the selector 11. a NOR gate 13 for generating a load control signal for the counter 12; a NOR gate 14 for generating a load control signal for the counter 12;
and a NANDA gate 15 for generating an enable control signal.

The decoding circuit 2 includes a decoder 21 that decodes the count value B of the IO bit counter 12 and outputs a signal E that causes the sub-counter circuit 3 to start counting.

In the main operation execution period signal generation circuit 3, the synchronization signal A is “H”°
The signal IQ (
A flip-flop (hereinafter abbreviated as JKFF) 31 is connected to J-, which outputs (positive logic) and IQ (negative logic), and signals 2Q (positive logic) and 2Q (negative logic) that indicate the time to execute the main operation.
a NOR gate 33 connected to the terminal of JKFF31, a NOR gate 34 connected to the J terminal of JKFF32, a NAND gate 35 connected to the NOR gate 34, and a terminal of JKFF32. NAND gate 36 connected to NOR gate 34 and NAND gate 34;
37 and a NOT gate 38 which inverts the carry signal C of the 10-pin counter 12 and inputs it to the NOR gate 33.
and a NOT gate 37 which inverts the synchronizing signal A and inputs it to the NAND gate 36.

The sub-counter circuit 4 includes a 4-bit counter 41 whose load value is the third parameter, a JKFF 42 for generating an enable control signal for the counter 41, and 1. JKF
A NOR gate 43 connected to the J terminal of F42,
NANDA-44 connected to the terminal of JKFF42
and NO to make the output signal E of the decoding circuit 2 an inverted signal.
T gate 45, NOT gate 46 which inverts the synchronizing signal A and inputs it to NANDA-to 44, and N which inverts the carry signal G of counter 41 and inputs it to NANDA-to 44.
OT gate 47.

The sub-operation execution period signal generation circuit 5 includes a JKFF51 that outputs a signal H indicating the time to execute the sub-operation;
NOR gate 52 connected to the J terminal of JKFF5
1, a NOT gate 54 that inverts the synchronizing signal A and inputs it to the NAND gate 53, and inverts the carry signal G of the 4-bit counter 41. explain. FIG. 2 shows the operation of the embodiment shown in FIG.

First, the operation of the main counter circuit 1 will be described.

By inputting the synchronization signal A to the NOR gates 13 and 14 in FIG. 1, the synchronization signal A becomes °H''.

When the state is reached, the first parameter is inverted via the selector 11, loaded into the counter 12, and initialized.

Since 1Q and 2Q are input to the NAND gate 15, the counter 12 continues counting from the time when the synchronizing signal A becomes "H" until the execution of the main operation is completed. After being loaded with the value corresponding to the first parameter, the counter 12, which continues counting, then sets the carry signal C to the "H" state. Carry signal C is NOR
The input is input to the gate 14, and the counter 12 is loaded again, but at that time, the selector 11 inputs I to the NOR gate 13.
Since Q is input, an inverted version of the second parameter is output to the counter 12. Then, after being loaded with the value corresponding to the second parameter, the counter 12
continues counting and sets the carry signal C to "H" again to end the counting.

Next, the operation of the main operation execution period signal generation circuit 3 will be described.

The 'H'° state of synchronization signal A is the initialization signal and JKFF31
input to the J terminal, NOR gate 33, and NOT gate 39, and when the synchronizing signal A becomes "H1", IQ becomes "H".
state, and 2Q becomes "'L"° state. counter 1
2 carry signal C is NANDA-to 35 and 37 and NO
Since IQ is connected to NANDA gate 35 and 2Q is connected to NANDA gate 37, IQ is in the '°H0 state and 2Q is ""L".
When the carry signal C becomes the °°H state under the "" state,
IQ changes to L11 state and 2Q changes to H'' state.

Then, when the carry signal C becomes H'' state, I
Q continues in the "L" state, and 2Q changes to the °'L" state. Through the above operations, 2Q becomes a gate signal indicating the period during which the main operation is executed.

Subsequently, the operation of the sub-counter circuit 4 will be explained.

Since the synchronization signal A is connected to the NOR gate 43 and the NOT gate 46, when the synchronization signal A becomes "'H" state, the Q output of JKFF42 is initialized to "1," state, and the NOT gate 45 becomes a load control signal for the counter 41, and by connecting the NOR gate 43, the output E of the decoding circuit 2 becomes °°H'"
When the state is reached, the counter 41 loads the third parameter 2, and when the Q output of the JKFF 42 becomes the °'H" state, the counter 41 starts counting.

Then, when the count value F of the counter 41 reaches the maximum, the carry signal G of the counter 41 goes into the high state, and the counter 41 stops counting. Then, when the output E of the decoding circuit 2 becomes "H" state again, the counter 41
loads the third parameter again, executes counting until the count value F reaches the maximum, and sets the carry signal G to “H1”.
1 state and stop counting.

Next, the sub-operation execution period signal generation circuit 5 will be explained. Since the synchronization signal A is connected to the NOR circuit 52 and the NOT circuit 54, the Q output of the JKFF 51, that is, the gate signal H indicating the period during which the sub-operation is executed, becomes "L" when the synchronization signal A enters the 14 state. When the carry signal G of the 4-bit counter 41 of the sub-counter circuit 4 becomes the "H++" state for the first time after the synchronization signal A becomes the "H" state, the period for executing the sub-operation is set. gate signal H
is in the °゛H°°H°° state, and when the carry signal G becomes the “14” state for the second time after the synchronization signal A becomes the “H” state, the gate signal H indicating the period for executing the sub-operation is activated. is ″L
“Return to state.

As is clear from the above explanation, the time when the sub-operation starts and the time when the sub-operation ends are determined by the decoder "output E of circuit 2".
This is a time corresponding to the third parameter after the current state becomes "H". That is, as shown by Δ in FIG. 2, by using the third parameter, the difference in the operation start time and the difference in the operation end time between the main operation and the sub-operation can be made variable, and the difference in the operation start time can be made variable. The difference and the difference in operation end time can be kept the same.

A, B, C, . . . , H in FIG. 1 correspond to A, B, C, . . . , H in FIG. 2, respectively. Further, T in FIG. 1 represents a clock, and R represents a reset signal.

In the above embodiment, the number of sub-operations is one, but the number of sub-operations may be plural. In this case, the count value B of the counter 12 in the main counter circuit 1 is input to a plurality of decoding circuits, and each Each of the decoding circuits may have a sub-counter circuit and a sub-operation execution period signal generation circuit, and the output of one decoding circuit may be input to a plurality of sub-counter circuits and a plurality of third parameters may be used. Thus, each sub-counter circuit may have a sub-operation execution period signal generation circuit.

(Effects of the Invention) As described above, according to the present invention, the main counter circuit and
A decoding circuit that decodes the count value of the main counter circuit, a sub-counter circuit that inputs the output of the decoding circuit as a start signal, and a sub-counter circuit that outputs the gate double angle without waiting for the period in which the sub-operation is realized by the output of the sub-counter circuit. The configuration includes an operation execution period signal generation circuit and a main operation execution period signal generation circuit that outputs a gate signal indicating the period during which the main operation is executed based on the output of the main counter circuit, allowing parameter input with a small number of bits. In addition, it is possible to obtain a timing generation circuit having a plurality of operations having the same operation execution period and differing only in operation start time with a small circuit scale.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a timing generation circuit according to an embodiment of the present invention, FIG. 2 is a diagram illustrating the operation of a timing generation circuit according to an embodiment of the invention, and FIG. 3 is a diagram illustrating a conventional timing generation circuit. , FIG. 4 is a diagram showing the operation of the conventional timing generation circuit of FIG. 3. 1... Main counter circuit, 2... Decode circuit, 3...
. . . Main operation execution period signal generation circuit, 4 . . . Sub counter circuit, 5 . . . Sub operation execution period signal generation circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) Signal that serves as a reference for operation (hereinafter referred to as synchronization signal)
In a timing generation circuit, there are multiple operations that are executed periodically, and the time to start the operation and the time to execute the operation can be set from the synchronization signal by parameters input from the outside. As an initialization signal, a clock with a constant frequency is used to count values corresponding to a first parameter that sets the time to start the main operation from the synchronization signal and a second parameter that sets the time to execute the main operation. The main counter circuit and the main operation execution period signal generation circuit, which generates a gate signal indicating the period during which the main operation is executed based on the output of this main counter circuit, are synchronized so that the operation execution time is the same as the main operation operation time. Decode the count value of the main counter circuit for sub-operations that differ only in the start time of the operation from the signal,
a sub-counter circuit that uses the decoded signal as a count start signal and counts a value corresponding to a third parameter that sets the difference in operation start time from the main operation using the same clock as the main counter circuit; 1. A timing generation circuit comprising: a sub-operation execution period signal generation circuit that generates a gate signal indicating a period in which the sub-operation is to be executed based on the output of the sub-operation execution period signal generation circuit.