JPH0368216A - Pll circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a PLL circuit that reproduces a sampling clock from an external synchronization signal in a video printer, etc. equipped with a function (auto scan function) to automatically follow the input signal frequency. It is.

[Conventional technology]

FIG. 3 is a diagram showing the configuration of a conventional PLL circuit, and the fourth
The figure shows the waveform of each signal according to FIG. 3, and the waveform number matches the number of each signal in FIG.

In the figure, l is a voltage controlled oscillator (hereinafter referred to as VCO), 2 is a sampling clock, and 3 is a frequency divider.
generate. 5 is an external synchronization signal of waveform 5 inputted from the outside. A comparator 6 compares the external synchronization signal 5 and the comparison synchronization signal 4 and outputs a signal having a waveform 7. 8
is a low-pass filter. 9 is an input control voltage of a vcoi waveform 9 obtained by passing the output signal 7 through a low-pass filter 8.

Next, the operation will be explained.

In FIG. 4, the comparator 6 outputs a signal having a waveform 7 based on the external synchronization signal 5 and the comparison synchronization signal 4. for example,
When an external synchronization signal 5, which is a standard signal such as NTSC or PAL, is input during period A, a signal having a waveform 7 shown in period A in FIG. 4 is output. The signal of waveform 7 is smoothed by a low-pass filter 8 and becomes a control voltage 9. The sampling clock 2 can be regenerated by inputting the control voltage 9 to the VCOI. Then, the sampling clock 2 is converted to an external synchronization signal 5 by a frequency divider 3.
A comparison synchronization signal 4 having the same frequency as that of

[Problem to be solved by the invention]

Since the conventional PLL circuit is configured as described above,
When a non-standard synchronous signal is manually input, for example, when a non-standard synchronous signal shifted from the normal position is input continuously as shown in period B in FIG. The resulting control voltage 9 in period B in FIG.
The comparison synchronization signal using the sampling clock generated only based on waveform 9 cannot fully follow the external synchronization signal, and the response of the sampling clock using vCO is slow, resulting in a printed image with a curved top. there were.

This invention was made in order to solve the above-mentioned problems, and it expands the variable range of the manually controlled voltage of the voltage controlled oscillator so that it can respond even when a non-standard synchronization signal is input. An object of the present invention is to obtain a PLL circuit that can improve response.

[Means to solve the problem]

The PLI circuit according to the present invention includes a pulse oscillator that generates a square wave pulse based on the output waveform of a comparator, a switch that switches the output of the pulse oscillator, and a switch control that generates a switch control pulse based on the output waveform of the comparator. It is provided with a circuit and an adder that adds and synthesizes the output signal from the pulse oscillator obtained by switching the switch to the output of the comparator.

[Function] The present invention includes a pulse oscillator that generates square wave pulses based on the output waveform of the comparator, a switch that switches the output of the pulse oscillator, and a switch control circuit that generates switch control pulses based on the output waveform of the comparator. and an adder that adds and synthesizes the output signal from the pulse oscillator obtained by switching the switch to the output of the comparator, so it can respond not only to standard synchronous signals but also to non-standard synchronous signals input manually. So the input control of the above voltage controlled oscillator? 1 [The variable range of voltage can be expanded, thereby making it possible to reproduce an accurate sampling clock without distortion in the output image, and improving the response of the sampling clock by vCO.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a PLL circuit according to an embodiment of the present invention, and FIG. 2 shows the waveform of each signal in FIG. 1, and the waveform number is the same as each signal in FIG. number and one loss.

In the figure, the same reference numerals as in FIG. 3 indicate the same parts. 1.
0 is a switch control circuit, which generates a switch control pulse 11 based on the output signal 7 of the comparator having a waveform 7. 12
is a switch for switching the signal output of the pulse oscillator 13, and is controlled by the control pulse 11 described above. 13
is a pulse oscillator, which generates a pulse 14 based on the output of the comparator. 15 is a pulse generated by switching the signal output of the pulse oscillator 13 with the switch 12; 16;
is an adder that adds together the pulse 15 and the output cuff of the comparator. Reference numeral 17 denotes a composite waveform signal synthesized by the adder 16.

Next, the operation of this embodiment will be explained.

The switch control circuit 10 uses the amplitude VI of the comparator output as a threshold point, is triggered at the rising edge of the pulse, and generates a square wave pulse having a certain pulse width. For example, in waveform 7 in Figure 2, at the rise of the first pulse, a pulse with the pulse width of period A is generated in waveform 11, and at the rise of the second pulse, a pulse of A having the same pulse width as A is generated. is generated, and if the period A is shorter than the period A, the waveform 11 continues to be in the OFF state.

Next, the period of waveform 1 is larger than the pulse width of waveform 1.
1 becomes ON after the period A. The waveform 11 created in this manner controls the ON10 FF of the switch 12.

The pulse oscillator 13 has an amplitude V as shown in waveform 7 in FIG.
2 is the threshold point and is triggered by the rising edge of the pulse to generate a pulse 14. Pulse 14 is ON10
Pulse 15 at switch 12 by F F signal 11
become. Then, the adder 16 adds the pulse 15 and the output cuff of the comparator.

The signals are combined into a composite waveform 17 signal. Thereafter, the synthesized waveform 17 becomes the control voltage 9 of the VCO 1 via the low-pass filter 8.

In this way, in this embodiment, the variable range of the control voltage input to the VCO is widened by changing waveform 7 to waveform 17 and widening the pulse width of waveform 9. As a result, non-standard The VCO can also respond to external input signals.
It is possible to improve the responsiveness of the image, and it is possible to obtain printed images without curves at the top.

In the above embodiment, when the positions of the external synchronization signal 5 and the comparison synchronization signal 4 are shifted two or more times in a row, the switch 12
The waveform 11 is created by ONf, .

Further, in the waveform 14 of FIG. 2, the force and force are equally spaced, and the duty ratio of the pulse waveform 14 is 1, but the duty ratio of the force and the force may be set to a value other than l.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a pulse oscillator that generates a square wave pulse based on the output waveform of a comparator, a switch that switches the output of the pulse oscillator, and a switch control pulse that generates a switch control pulse based on the output waveform of the comparator. A switch control circuit and an adder that adds and synthesizes the output signals from the pulse oscillator obtained by switching the switch to the output of the comparator are provided, so it can handle not only standard synchronous signals but also non-standard synchronous signals input. To make it possible to widen the variable range of the input control voltage of the voltage controlled oscillator, reproduce an accurate sampling clock without distortion in the output image, and improve the responsiveness of the VCO to non-standard external synchronization signals. This has the effect of producing normal printed images.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a sampling clock recovery circuit of a PLL circuit according to an embodiment of the present invention, FIG. 2 is a timing chart diagram for explaining the operation of the present invention, and FIG. 3 is a diagram depicting a conventional PLL circuit. , FIG. 4 is a timing chart diagram for explaining the operation of the conventional circuit. l is a voltage controlled oscillator (VCO), 2 is a sampling clock, 3 is a frequency divider, 4 is a comparison synchronization signal, 5 is an external synchronization signal, 6 is a comparator, 7 is the output of the comparator, 8 is a low-pass filter, 9 is a control voltage, lO is a switch control circuit, 11
12 is a switch control pulse, 12 is a switch, 13 is a pulse oscillator, 14 is a pulse, 15 is a switch output, 16 is an adder, and 17 is a composite waveform. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A voltage controlled oscillator that reproduces a sampling clock for quantizing an analog video signal by following the horizontal frequency change of an external synchronization signal, and a comparison synchronization signal for comparing the sampling clock with the external synchronization signal. a frequency divider that generates a frequency divider, a comparator that compares the comparison synchronization signal with an external synchronization signal, and outputs a pulse that is the basis of the control voltage of the voltage controlled oscillator; A PLL circuit including a low-pass filter that generates a control voltage to be input to the controlled oscillator, and a pulse oscillator that generates a square wave pulse according to the output pulse waveform of the comparator, and a pulse oscillator that generates a square wave pulse according to the output pulse waveform of the comparator, and a switch for switching the pulse output of the pulse oscillator; a switch control circuit for generating a pulse for controlling the switch based on the output pulse of the comparator; A PLL circuit comprising an adder for adding and synthesizing output pulses from the pulse oscillator obtained by switching a switch to the output pulses.