JPH0368232A - Digital phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To generate a clock, which can send a transmission signal of less jitter to a home device and has less jitter, in an intra-office terminating equipment by providing a master clock oscillator, a frequency division ratio designating circuit, a variable frequency dividing circuit, or the like. CONSTITUTION:The master clock from a master clock oscillator 1 has the frequency normally divided by N in a variable frequency dividing circuit 2 to generate an output clock, and this output clock is outputted to a fixed frequency dividing circuit 3. The circuit 3 outputs the inputted clock to a phase comparing circuit 4 after frequency division, and the circuit 4 compares its phase with the phase of the reference clock extracted from a network. The frequency division ratio of the circuit 2 is changed by a frequency division ratio designating circuit 5 in accordance with the comparison result to synchronize the phase. In this case, a frequency fM of the master clock is set to satisfy fM=f0XN+ or fM =f0XN- where f0 is the nominal frequency of the output clock. Thus, the frequency in occurrence of jitter is reduced to improve the circuit characteristic.

Description

[Detailed Description of the Invention] [Summary] Regarding a digital phase synchronization circuit of an in-office termination device that creates the timing of a transmission signal to an in-home device in a digital subscriber line transmission system, the in-office termination device transmits a transmission signal with less jitter to the in-home device. The purpose is to create a clock with low jitter that can be sent to a device.The frequency of the master clock is divided to create an output clock, and the phase of the output clock is determined by dividing the phase of the reference clock extracted from the network. In a digital phase synchronized circuit that compares the phase and changes the division ratio to match the phase of the output clock with the phase of the reference clock if there is a difference in phase, N of the nominal frequency (f0) of the output clock is used. times + Δ or N times Δ (Δ is a small value)
a master clock oscillator that outputs a master clock having one of the frequencies (fM4); and a master clock that receives the master clock from the master clock oscillator and outputs the master clock according to the division ratio specified value that is input from the division ratio specification circuit. A variable frequency divider circuit that divides the frequency of 1 to 1 of the frequency specified by the division ratio and outputs it as an output clock, and divides the output clock from the variable frequency divider circuit and inputs the branched clock, a fixed frequency divider circuit that divides the frequency by a frequency ratio (fo/fs) of the frequency and the reference clock and outputs it as a phase comparison clock; and a phase comparison clock output from the fixed frequency divider circuit and the reference clock. A frequency division ratio change instruction for inputting a clock and comparing the phases, and changing the frequency division ratio of the variable frequency divider circuit when the phase lead/lag relationship between the phase of the phase comparison clock and the reference clock is reversed. A phase comparator circuit that outputs a signal to the frequency division ratio designation circuit (5) and a phase comparison circuit that stores two types of frequency division ratio designation values that designate the frequency division ratio of the variable frequency division circuit (12). supplying a reference value N as a designated value to the variable frequency divider circuit;
When the frequency division ratio change instruction signal is received from the phase comparator circuit, if the frequency (f) of the master clock is set to N times the nominal frequency (f0) of the output clock + Δ, it is greater than the reference value. Frequency division ratio specified value (N+1), N
When set to times −Δ, the frequency division ratio designation circuit is configured to supply a frequency division ratio designation value (N-1) smaller than the reference value to the variable frequency division circuit.

[Industrial Field of Application] The present invention relates to a digital phase synchronization circuit for an in-office termination device that creates timing of a transmission signal to an in-home device in a digital subscriber line transmission system.

The subscriber system in digital transmission systems consists of an in-office terminating unit (OCU) installed in the office and a in-home terminating unit (DSU) installed in the customer's home. It is necessary to be synchronized to the network in order to transmit and receive. For this reason, the in-office terminal device is equipped with a phase locked loop (PLL) as a device for synchronizing the transmission timing with the network.

The phase synchronization circuit is a circuit that creates a clock synchronized with a reference clock input from a network, and there are analog types that use a voltage-controlled oscillator and digital types that control the frequency division ratio of a high-speed master clock. .

In the analog type, the oscillation frequency itself of the oscillator matches the network reference clock, so it is possible to obtain jitter-free transmission timing with respect to the network reference clock. However, to create the control voltage for a voltage controlled oscillator,
Digital LSI
There is a problem in that it is difficult to integrate the device into a device, making it difficult to make the device smaller and more economical.

On the other hand, digital phase-locked circuits can be integrated on digital LSIs, but the output clock is created by dividing the frequency of the master clock, and when a phase difference with the network reference clock occurs, , master clock 1
Since the phase adjustment is performed by changing the frequency division ratio using the period as the minimum unit, the output clock always causes jitter with respect to the network reference clock. Therefore, the transmitted signal has jitter, which is one of the causes of deterioration in timing recovery on the receiving side.

In view of the above, there is a need for a digital phase synchronization circuit that is easy to integrate and has low jitter.

[Conventional technology]

FIG. 3 is a circuit diagram of a conventional digital phase synchronization circuit.

In FIG. 3, a master clock from a master clock oscillator 21 having a frequency f is input to a counter 22, which is normally 1/1/2.
An output clock is created by dividing the frequency by N, and the output clock is further divided by 1/M in the 1/M frequency dividing circuit 23, and then the phase is compared with the reference clock. Set the division ratio to 1/(N+1) or l/(
This is a circuit that performs phase synchronization by changing the phase to N-1).

If the frequency of the reference clock extracted from the network is 1°, the frequency of the output clock is 1° (.≧Is), and the frequency of the master clock is f, then in the normal state, r, -r. /N.Furthermore, since the output frequency of the l/M frequency dividing circuit 23 is made to almost match the frequency f of the reference clock for phase comparison, it becomes f,Zfo/M-r8/NxM. Therefore, if the phase is shifted because the reference frequency and the output frequency do not match, the phase can be made to match f by changing the value of N in f,/NxM.

The counter 22 performs counting by inputting the master clock from the master clock oscillator 21 to the CK terminal, and usually divides the frequency of the master clock into l/N by sending an output every time N master clocks are counted. Create an output clock with a frequency of fo-f, /N. Specifically, the counter 22 counts the master clock using a multi-digit binary number, and selects an initial value for starting binary counting in order to set an arbitrary number N using the selector 25.
The signal is input to the D terminal of the counter 22 via. For example, when outputting a clock divided by 1/10 of the master clock using a 4-digit binary number, the data A input to the selector 25 corresponds to "6°" in the 10-based number starting from "0". It is set as a binary number and connected to the D terminal of the counter 22 via the selector 25. When the counter 22 counts the master clock and all four-digit binary numbers become l,
That is, when the lO base value reaches '15°', a carry-out signal is sent from the CO terminal of the counter 22 to the LD terminal, and the count value of the master clock is restored to the value of the D terminal. Because the base number “6pa” is input,
The counter 22 repeats counting from decimal degrees 6 to 15''.

The most significant digit of the binary number of the internal counting circuit is connected to the Q7 terminal of the counter 22, and the output turns on the output of the Qn terminal when the most significant digit of the binary number becomes 1 during counting. This is done by doing this. In the above example, “°9” in lO base
', but the most significant digit turns on once every 10 master clocks are counted, so the Qfif child of the counter 22 turns on when the master clock 10
It is turned on each time a piece is counted, and the master clock is set to 1.
Sends out an output clock whose frequency is divided by /10.

The output clock of the counter 22 is further divided by 1/M in the 1/M frequency dividing circuit 23 to become a clock having almost the same frequency as the reference clock as described above, and is inputted to the phase comparison circuit 24 for phase comparison with the reference clock. It is done.

Based on the result of the phase comparison, the phase comparison circuit 24 generates a phase control signal that instructs whether or not to perform phase control according to preset conditions, and a lead/lead signal that specifies whether to advance or delay.
A delay designation signal is created and output to the selector 25. The selector 25 normally selects data 8, but when performing phase control, control is performed so that data (A+1) is selected when advancing and data (A-1) is selected when delaying.

In the above example where the master clock outputs a clock divided by 1/10 using a 4-digit binary number, since A is "6", the data (A+1) is used to advance by phase control.
is selected, “7°°” is input to the D terminal, and the counter 22 returns to 7° when carry-out occurs, and lO
Nine master clocks from "7°" to "15" in base numbers are counted and carried out. In other words, 1/
The frequency is divided by 9, and the phase of the output clock advances by one period of the master clock. When delaying, this is reversed, and the counter is frequency-divided by 1/(N+1) to delay the phase of the output clock by one cycle of the master clock, thereby synchronizing the output clock with the network reference clock.

On the other hand, it is known that the oscillation frequency of an oscillator varies depending on the ambient temperature, power supply voltage, etc., and in the case of an oscillator using a crystal resonator, there is a variation range of about ±100 ppa+. The frequency accuracy of the master clock is also the same as above, but on the other hand, since the network reference clock is extremely accurate, the frequency of the master clock is divided by the master clock oscillator. There is a high possibility that the phase of the clock will lead or lag behind the reference clock. In addition, even if the same master clock oscillator is used, it may be biased in either direction due to fluctuations in temperature, power supply voltage, etc., so if a master clock oscillator is used in which the phase of the output clock and the phase of the reference clock match, Of course,
Even when using a master clock oscillator whose frequency is biased either high or low, there is a possibility that the phase of the output clock moves both ahead and behind the reference clock. For the reasons described above, whenever the phases shift, it is necessary to perform phase control of the output clock in a direction that digitally matches the phases.

In the conventional system, a master clock having a frequency N times that of the output clock is used, so the frequency of the clock obtained by dividing the master clock and the frequency of the reference clock almost match. Therefore, the possibility that the phase of the output clock will lead or lag with respect to the reference clock is greater than the possibility that it will lead or lag only. In a digital phase synchronization circuit, phase control is performed in the direction of correcting the lead/lag every time there is a phase shift. Therefore, the output clock of the conventional method has one cycle of the master clock before and after the reference clock, for a total of two cycles. Jitter may occur.

Also, even if phase control is performed, it is difficult to perfectly match the frequencies of the reference clock and output clock, so
When a phase comparison is performed, the phases of the reference clock and the output clock rarely match completely, and in most cases they are slightly out of phase. That is, in the conventional method,
Every time the reference clock is input, the phase of the output clock is controlled, and the frequency of jitter will not be lower than the frequency of the reference clock, so the frequency of the reference clock must be sufficiently low compared to the frequency of the output clock. If not, it will affect the timing recovery on the receiving side of the output clock.

[Problem to be solved by the invention]

As described above, in conventional digital phase synchronization circuits, the master clock is N times the output clock, so the frequency deviation of the master clock oscillator causes the phase of the output clock to change in both directions. jitter occurs with a width of two cycles of the master clock, and the frequency of jitter occurrence does not fall below the frequency of the reference clock, which affects timing recovery on the receiving side.

SUMMARY OF THE INVENTION An object of the present invention is to create a clock with less jitter in an in-office terminal device that can send a transmission signal with less jitter to an in-home device.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention.

In the figure, ■ is N times the nominal frequency (f0) of the output clock +
A master clock oscillator that outputs a master clock with a frequency (fM) of either Δ or N times − Δ (Δ is a small value), 2 inputs the master clock from the master clock oscillator 1, and specifies the division ratio. A variable frequency divider circuit 3 divides the frequency of the master clock into a frequency of 1 of the frequency division ratio designation circuit according to the frequency division ratio designation value inputted from the circuit 5, and outputs it as an output clock; 3 is the variable frequency division circuit 2; The output clock of the output clock is branched and inputted, and the frequency ratio (f
A fixed frequency divider circuit 4 divides the frequency by 1/fs) and outputs it as a phase comparison clock, and 4 inputs the phase comparison clock output from the fixed frequency divider circuit 3 and the reference clock to calculate the phase. A frequency division ratio change instruction signal for changing the frequency division ratio of the variable frequency dividing circuit 2 when the lead/lag relationship between the phase of the phase comparison clock and the phase of the reference clock is reversed. A phase comparator circuit 5 outputs to the designation circuit 5, which stores two types of frequency division ratio designation values that designate the frequency division ratio of the variable frequency division circuit 2, and usually uses a reference value N as the frequency division ratio designation value. is supplied to the variable frequency divider circuit 2, and when a frequency division ratio change instruction signal is received from the phase comparator circuit 4, the frequency (L+) of the master clock becomes N times the nominal frequency (f0) of the output clock + Δ If set to , the specified dividing ratio value (N+1) or N times - is larger than the reference value.
If it is set to Δ, it is a frequency division ratio designation circuit that supplies the frequency division ratio designation value (N-1) smaller than the reference value to the variable frequency division circuit 2.

[For production]

In FIG. 1, a master clock from a master clock oscillator 1 is normally divided by 1/N in a variable frequency divider circuit 2 to create an output clock, and the output clock is divided in a fixed frequency divider circuit 3. A phase comparison circuit 4 compares the phase with the basic clock extracted from the network,
Depending on the comparison result, the frequency division ratio of the variable frequency divider circuit 2 is changed via the frequency division ratio specifying circuit 5 to perform phase synchronization.

In this case, the nominal frequency of the output clock is fo, and the frequency of the master clock is f. Then, fx = fo x
The frequency f8 of the master clock is set so that N+Δ or r,4=f6XN−Δ, but below, a case where it is set so that f,=f0xN−Δ will be explained.

In addition, in order to compare the phase of the reference clock extracted from the network and the output clock, the frequency r of the reference clock must be
It is necessary that o and the frequency ro of the output clock match, but if this is not the case, the frequency of the output clock is divided into 1/M (M=f, /f,) in the fixed frequency divider circuit 3. The clock is rotated to create a phase comparison clock and match the frequency with the reference clock. However, in the following description, for convenience of explanation, it is assumed that f,=f, and there is no fixed frequency divider circuit 3 with M=1.

The variable frequency divider circuit 2 inputs the remaster clock from the master clock oscillator l and performs counting, and the frequency division ratio specifying circuit 5
If the designated frequency division ratio value inputted from is N, an output clock is sent out every time N master clocks are counted. Set the frequency of this output clock to 1. Then, fA - (rs /N) - (ro lower than the nominal frequency ro. In the conditions of this example, fo-f, so
The frequency ft of the output clock is the frequency ro of the reference clock
, and the period of the output clock becomes larger than the period of the reference clock. Therefore, when the output clock is input to the phase comparator circuit 4 and its phase is compared with the reference clock, the phase of the output clock gradually lags behind the reference clock. Therefore, even if the phase of the output clock input to the phase comparison circuit 4 is initially ahead of the reference clock, a situation occurs where the phase of the output clock lags behind the reference clock while the phase comparison is being performed.

In the present invention, as described above, since a reversal always occurs in the phase lead/lag relationship between the reference clock and the output clock, when the phase is reversed, the phase comparison circuit 4 transmits the division ratio change instruction signal to the division ratio specifying circuit. Output to 5.

The frequency division ratio designation circuit 5 stores two types of values as frequency division ratio designation values: a reference value N and a value smaller than the reference value (N-1).
Normally, the reference value N is output to the variable frequency divider circuit 2, but when the frequency division ratio change instruction signal is received from the phase comparator circuit 4, a frequency division ratio designated value of (N-1) is outputted.

The variable frequency divider circuit 2 normally outputs an output clock obtained by dividing the master clock by 1/N, but when it receives a designated frequency division ratio value of (N-1), it divides the frequency by 1/(N-1). Since the 0 frequency division ratio for transmitting the output clock becomes lower by 1, the variable frequency divider circuit 2 transmits the next output clock earlier by one period of the master clock. Therefore, if the frequency and N of the master clock are set appropriately, when the frequency division ratio change instruction is given, the phase of the output clock will lead the phase of the reference clock. The comparator circuit 4 returns the designated frequency division ratio value to the reference value N, and performs phase comparison every time the reference clock is input, but does not perform phase control even if the output clock gradually lags behind the reference clock unless it lags behind the reference clock. . That is, since phase control is no longer performed every time the reference clock is input, the frequency of occurrence of jitter is reduced.

Above, the master clock frequency ``, fH=fo
Although the case where the setting is made to be xN-Δ has been described, the same applies to the case where the setting is made to be 1.4=fo xN+Δ.

In addition, in the above, the frequency of the output clock and the reference clock are the same, but if the frequency of the output clock is higher than the reference clock, the frequency of the output clock is divided by the fixed frequency divider circuit 3 to match the frequency of both clocks. It is clear that the same effect as above can be obtained by increasing the amount of water.

As explained above, in the present invention, either N times + Δ or N times − Δ of the nominal frequency of the output clock is used as the frequency of the master clock, so the phase of the output clock can only lead or lag. , the jitter is within the width of one cycle of the master clock, and the frequency of sick occurrence is determined by the difference between the master clock frequency and the reference clock frequency and the fluctuation width of the master clock frequency, and the phase control is performed each time the reference clock is input. Since it is not necessary to perform this process, it is possible to reduce the frequency of occurrence of jitter.

〔Example〕

FIG. 2 is a circuit diagram of one embodiment of the present invention.

In the figure, 11 is a master clock oscillator, 12 is a counter, 13 is a frequency dividing circuit, 14 is a phase comparison circuit, and 15 is a selector.

FIG. 2 shows an example in which the counter 12 outputs a clock obtained by dividing the master clock by 1/96 in the normal state, and the frequency fs of the reference clock, the nominal frequency 10 of the output clock, and the frequency 18 of the master clock are each below. It shows.

fs = 8 (kHz) fo = 160 (kHz) fH = 160 x 96-100 ppm (kHz
z) -15,358464 (MHz) That is, the master clock oscillates at a frequency 100 ppm lower than 96 times the nominal frequency of the output clock, so the frequency rA of the output clock of counter 2 is f A = 15.358464/96 (MHz
)=159.984 (kHz). The output clock is further divided into 1/20 by frequency dividing circuit 1-15-
The frequency of the phase comparison clock divided into f a /2
0=7.9992 (kHz),
8 of the reference clocks compared in the phase comparator circuit 1+
The frequency is slightly lower than kHz.

Counter 2 performs counting by inputting the master clock to the CK terminal, and in the normal state, the mask-clock 9
An output is sent every time 6 is counted, but in order to count 96, a 7-bit binary number that can be displayed up to 128 in decimal is required, so the output terminal Qfi is set to 7 in binary.
Outputs bit on/off. Also, counter 2
The D terminal consists of 7 terminals, and a 7-digit binary number is input, but in this example, the decimal number 128-96= is input to the D terminal.
A binary number corresponding to 32 is input. Therefore, in the normal state, the data A selected by the selector -L4→ is a binary number equivalent to 32, and the data (A+1) is 3.
It becomes a binary number equivalent to 3.

When data A is input to the counter 2 via the selector 15, the counter 2 counts the master clock, and every time there is a carry-out, a low signal is sent from the CO terminal.
An output is sent to the D terminal, the count value is restored to the value of the D terminal, that is, the value of data A, and 96 master clocks are counted until the next carryout. During this time, each time the most significant bit of the count turns on, the Qfi terminal is turned on and an output clock is sent out.

The output clock of the counter 2 is input to the frequency divider circuit 13, and further divided by 1/20 to create a phase comparison clock having almost the same frequency as the reference clock as described above, and input to the phase comparison circuit 14. A phase comparison with a reference clock is performed. As a result of the phase comparison, the phase comparator circuit 14 does not perform phase control if, for example, the phase of the output clock is ahead of the phase of the reference clock, and when the phase of the output clock lags behind the phase of the reference clock, the phase comparator circuit 14 performs frequency division control. Sends a ratio change instruction signal. Upon receiving the frequency division ratio change instruction signal, the selector 15 changes the selection from data A to data (A+1) and supplies it to the D terminal of the counter 12.

In the counter 12, when a binary number corresponding to decimal number 33 is inputted as data (A+1), when it is carried out during counting, counting starts from 33, so the frequency is divided into l/95. The phase of the next output clock advances by one cycle of the master clock, and the phase of the output clock also advances in phase with respect to the reference clock in the phase comparator circuit 14.

Thereafter, the phase comparison circuit 14 performs phase comparison every time the reference clock is input, but does not perform phase control even if the output clock gradually lags behind the reference clock as long as it does not lag behind the reference clock.

In the above embodiment, the frequency f of the master clock is set to r
Although we have explained the case where it is set lower than ,xN, r,
f. It is clear that similar effects can be obtained even if the value is set higher than XN.

In addition, although the frequency of the reference clock is 8 k)lz and the nominal frequency of the output clock is 160 kHz, these frequencies can be arbitrarily selected, and the dividing ratio of the frequency dividing circuit 13 can be adjusted as appropriate. By selection, it is also possible to arbitrarily set the ratio between the frequency of the reference clock and the nominal frequency of the output clock.

Although the present invention can be modified in various ways as described above, the present invention does not exclude these modifications.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional system. In the figure, ■ 2 ・−111・・−−−−1−・−・3−・・−−−
−・4−・−・−１−−−−−−−−−−=・. Master Clock Oscillator Variable Frequency Divider Circuit Fixed Frequency Divider Phase Comparator Circuit Divider Ratio Designation Circuit (Effects of the Invention) As explained above, according to the present invention, the jitter of the output clock is kept within the width of one cycle of the master clock, In addition, since there is no need to perform phase control each time the reference clock is input, it is possible to reduce the frequency of jitter occurrence.
This greatly contributes to improving the characteristics of such digital phase-locked circuits. Powder circumference ratio M=fo/Ts) Fig.

Claims (1)

[Claims] An output clock is created by dividing the frequency of a master clock, and the phase of the output clock is compared with the phase of a reference clock extracted from a network. In a digital phase synchronized circuit that matches the phase of the output clock with the phase of the reference clock by changing the division ratio, the nominal frequency (f_0) of the output clock is N times + Δ or N times − Δ (Δ is a small value). One of the frequencies (f_
a master clock oscillator (1) that outputs a master clock having a clock frequency M); and a master clock oscillator (1) that receives the master clock from the master clock oscillator (1) and outputs the master clock according to the division ratio designation value input from the division ratio designation circuit (5). A variable frequency divider circuit (2) that divides the frequency of a master clock into a frequency divided by a specified frequency division ratio value and outputs it as an output clock; and the variable frequency divider circuit (2).
The output clock is branched and inputted, and the frequency ratio (f_0
A fixed frequency divider circuit (3) that divides the frequency by 1/f_S) and outputs it as a phase comparison clock, and inputs the phase comparison clock output from the fixed frequency divider circuit (3) and the reference clock. a frequency division ratio change instruction signal for changing the frequency division ratio of the variable frequency division circuit (2) when the phase of the phase comparison clock and the reference clock are reversed in lead/lag relationship; a phase comparison circuit (4) that outputs the frequency division ratio to the frequency division ratio designation circuit (5), and stores two types of frequency division ratio designation values that designate the frequency division ratio of the variable frequency division circuit (2); Normally, a reference value N is supplied to the variable frequency divider circuit (2) as a frequency division ratio specified value, and when a frequency division ratio change instruction signal is received from the phase comparator circuit (4), the frequency of the master clock ( f_M) is set to N times + Δ of the output clock's nominal frequency (f_0), the specified frequency division ratio value (N+1), which is larger than the reference value, is N times -
The frequency division ratio designation circuit (5) supplies the frequency division ratio designation value (N-1) smaller than the reference value to the variable frequency division circuit (2) when the frequency division ratio designation value (N-1) is set to Δ. Digital phase synchronization circuit.