JPH0368422B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a data transfer control method for controlling data transfer from a memory to a processing device in a processing system.

(b) Prior Art and Problems In a processing system in which a processing unit and memory are connected via a local bus, and an external control register, etc. is connected to the local bus via a transmitting/receiving circuit, the external control register, etc. etc., the line length of the local bus becomes long, causing signal delay during data transfer. As mentioned above, the processing device and memory are connected via this local bus, so when data in the memory is read and transferred by a read command from the processing device, in the conventional method, the read data There was a drawback that the data could not be transferred to the processing device at high speed.

(c) Purpose of the Invention The present invention was made to solve the above-mentioned drawbacks, and its purpose is to provide a data transfer control system that facilitates high-speed data transfer.

(d) Configuration of the Invention A transmitter/receiver circuit TR1 is connected via a first high-speed bus 1 to a memory control unit 7 that controls reading/writing of the memory 8 and a processing device 6 that issues a read request to the memory. and common bus 1 to input/output device 12.
In a system in which a transmitter/receiver circuit TR3 connected via a transmission/reception circuit TR3 is connected via a local bus 2, one end is connected to the local bus 2, and the other end is connected to the memory control unit 7 via a second high-speed bus 3. a connected first drive circuit D1, one end of which is connected to the memory control unit 7 via the second high-speed bus 3;
The other end is connected to the processing device 6 via the first high-speed bus 1, and the second drive circuit D2 is composed of high-speed elements. The drive circuit D2 is enabled, and the first
and a transfer control unit 9 that enables the drive circuit D1 of the first high-speed bus 1 and the second high-speed bus 3 in response to a memory read request from the processing device 6.
Transfer data from the memory 8 using
A data transfer control system characterized in that in response to a memory read request from the input/output device 12, data is transferred from the memory 8 using the second high-speed bus 3, the local bus 2, and the common bus 10. It is.

(e) Examples of the invention The present invention will be explained below with reference to the drawings. The drawing is a block diagram illustrating an embodiment of the present invention.
The transfer control unit 9, valid signal C ₂ , and driver D ₂ in the drawings are parts added according to the present invention. A processing device (microprocessor) 6 is connected by a bus 1 to a transmitter/receiver circuit TR ₁ and a driver (drive circuit composed of high-speed elements) D ₂ . The transmitting/receiving circuits TR ₁ , TR ₂ , TR ₃ , driver D ₁ and memory control section 7 are connected by a bus 2, while an external control register 11 is connected to the transmitting/receiving circuit TR ₂ . In the conventional method, data E in the memory 8 is read out via the receiver R, subjected to an error check by the memory control unit (including error check circuit) 7, and then sent to the bus 2 via the bus 3 and driver _D1 . . This data E is processed by the processing device 6
When a read request is issued from the transmitter/receiver circuit TR ₁ and the bus 1, it is sent to the processing device 6, or when a write request to the external register 11 is issued from the processor 6, it is sent to the transmitter/receiver circuit TR. ₂ , and is sent to the external register 11. Bus 2 is
When there are many external control registers, etc., the line length becomes long, causing a signal delay during data transfer. Therefore, even when the processing device 6 issues a read request for the data E in the memory 8, the data E is transferred to this bus 2.
Therefore, there was a drawback that data transfer between the processing device 6 and the memory 8 could not be performed at high speed.

In the drawing, when a read request F is issued from the processing device 6, the transfer control unit 9 enables the driver _D2 by the enable signal _C2 . The data E read from the memory 8 undergoes an error check in the memory control section 7, and then is sent to the processing device 6 via the bus 3, driver _D2 , and bus 1. As is clear from this, when a read request F is issued from the processing device 6, the data E read from the memory 8 is transferred via buses 3 and 1 (not via bus 2), resulting in high-speed data transfer. It can be performed. Note that when the read request G is issued from the input/output control channel 12, the transfer control unit 9 enables the driver _D1 by the enable signal _C1 . The data E read from the memory 8 is sent to the memory control unit 7, the bus 3,
The signal is sent to the input/output device via the driver D ₁ , the bus 2, the transceiver circuit TR ₃ , and the common bus 10.

(f) Effects of the Invention As described above, the present invention has a means for transferring data between a processing device and a memory at high speed, and therefore has the advantage of significantly improving the processing efficiency of a processing system.

[Brief explanation of drawings]

The drawing is a block diagram illustrating an embodiment of the present invention, and the symbols used in the drawing are as follows. 1 and 3 are buses, 2 is a local bus, 6 is a processing unit, 7 is a memory control unit, 8 is a memory, 9 is a transfer control unit, 10 is a common bus, 11 is an external control register, C ₁ and C ₂ are valid Signal, D ₁ , D ₃ are drivers or drive circuits, D ₂ is drivers (high speed) or drive circuits, E is data, F, G are read requests, R is receiver, TR ₁ , TR ₂ , TR ₃ are transmission/reception The circuit, 12, indicates an input/output control channel.

[Claims]

1 A plurality of terminal devices and at least one bus control device are connected via one serial data bus line, and data transfer between the terminal devices and data transfer between the terminal device and the bus control device are performed. In a command-response serial multiplex data bus system in which data transfer is controlled by the bus control device based on a command transmitted from the bus control device and a response returned from the terminal device, the terminal device transmits an interrupt request to the bus control device including an internally generated alarm data transmission request and a data reception request via the data bus line, and transmits the data controlled by the bus control device. As a method for changing the transfer schedule, the terminal device includes a means for transmitting and receiving data via the data bus line, a means for detecting the end of data transfer on the data bus line, and a means for detecting the end of the transfer. During the period up to the beginning of the command, which is the start of the next data transfer, the split is performed using a frequency band outside the frequency band for data transfer and with an amplitude lower than that of the data.