JPH0368539B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an integrated circuit using a bipolar transistor exhibiting unsaturated current-voltage characteristics with a base forward bias configured such that the base region is almost pinch-off and the effective base width is sufficiently thin. Concerning novel structures of circuits.

In conventional integrated circuits, bipolar transistors (hereinafter referred to as BPTs) are used in logic gate sections that require high-speed operation. Although BPT operates at high speed, it consumes more power and has lower input impedance than MOS field effect transistors (hereinafter referred to as MOSFETs).
It has a fatal drawback in that it cannot be directly connected to the next stage, so it cannot achieve a high degree of integration, making it disadvantageous for use in semiconductor integrated circuits that require a high degree of integration. Furthermore, the operating speed of BPT is limited by the large area between each electrode and the significant accumulation effect of minority carriers injected into the base. Aside from these drawbacks of BPT, it has high input impedance and can be directly connected to the next stage, the capacitance between each electrode is small, the conversion conductance is quite close to that of BPT, and it has a large drive capacity and high-speed operation. , the inventor proposed and developed a static induction transistor as a transistor that can achieve a large number of fan-outs.
It has been successfully applied to integrated circuits such as BPT's I ² L (Integrated Injection Logic) (Patent No. 1181984 (Special Publication No. 11102)) ``Semiconductor integrated circuit'', Patent No. 1208034 (Special Publication No. 1983-11102). −38938)
"Semiconductor Integrated Circuits", Proceedings of the International Conference on Solid State Devices, September 1-3, 1975, pp. 53-54).

The fact that a transistor in which the vicinity of the gate region is almost pinched off with a reverse bias applied to the gate causes a spatio-temporal charge limited current to flow and exhibits unsaturated current-voltage characteristics means that as an individual device, R.
This was known by Zuleeg et al. (US Pat. No. 3,409,812), but it exhibited saturated current-voltage characteristics when a forward bias was applied to the gate.

The present invention uses an EFL (Emitter Follwer Logic) integrated circuit for BPT, which exhibits unsaturated current-voltage characteristics in forward bias, to create a new integrated circuit that has a small minority carrier accumulation effect, good frequency characteristics, and high-speed operation. The purpose is to provide a structure.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an example of the cross-sectional structure of an AND gate with three inputs and two outputs. Figure 1 shows an example where lateral impurity diffusion occurs in the ^p region.
1', n ^- region 2 is the collector of the output npn-BPT, p
Regions 4, 51, 52 and n ⁺ regions 13, 23 are the base and emitter of the output npn-BPT, respectively,
P region 6 is the emitter of input pnp-BPT, n regions 7, 17, 27, 37, 8 are the base, p region 9,
9' is a collector. 10 is an insulating layer, 31, 3
2 is an output electrode, 71, 72, 73 are input electrodes,
6' is the first wiring layer connecting the base of the npn-BPT and the emitter of the pnp-BPT, and 18 is the npn-BPT.
This is the second wiring layer for power supply connected to the collector of. Although not shown, 6' and 18 are connected via a resistor (Rc). 9' is grounded by an electrode on the back side of the substrate. Area 13,2
The impurity density of 3,6 is about 10 ¹⁸ ~ 10 ²¹ cm ^-3 , 1,
1', 9' are about 10 ¹⁷ to 10 ²⁰ cm ^-3 , 4, 7, 17,
27, 37 is about 10 ¹⁶ ~ 10 ²¹ cm ^-3 , 51, 52,
8 is about 10 ¹² to 10 ¹⁶ cm ^-3 , 2 and 9 are about 10 ¹² to 10 ¹⁷ cm ^-3
That's about it. Reference numeral 11 forms an isolation region using insulating polysilicon or insulating resin. In order to operate, the base regions 51 and 52 existing between the emitter and collector of the npn-BPT must almost become a depletion layer due only to the diffusion potential of the n ⁺ p or n ^- p contact. Since the bases 51 and 52 existing between the emitter and the collector are formed by diffusion from the p region 4, their impurity density is naturally lower than that of the original region 4. Similarly, the base region 8 of pnp-BPT is n ⁺ region 7, 17,
The impurity density is lower than that of 27 and 37, and the p ⁺ n junction with the emitter region 6 and the collector region are almost depleted layers due to only the diffusion potential of the np junction with the emitter region 6. Therefore, in the structure shown in FIG. 1, the base regions 51, 52, and 8 are quite thin and have a low impurity density, and the base regions 51, 52, and 8 almost become depletion layers only due to the diffusion potential generated at the contact portion with the opposite conductivity type region. It's almost in a pinch-off state. When the base region is in a pinch-off state, the potential of the base region approaches the potential of the opposite conductivity type regions on both sides of the base region. The potential has not approached the potential of the region of the opposite conductivity type, and a potential barrier still exists, and its thickness is sufficiently thin to control the amount of carrier injection from the emitter to the base. The state is defined as a state in which the base is almost pinched off.
If the thickness and impurity density of the base region are selected to achieve this state, the carriers flowing from the emitter to the collector will be injected into the collector side over the potential barrier, just like in the case of a static induction transistor, and will drift. The behavior is almost the same as multiple carrier injection, and the conventional
The effect of minority carrier accumulation in the base region due to minority carrier injection in BPT does not appear. Due to the presence of the base regions 51, 52 and 8 described above, it is easy to create a normally-off type even if the channel length between the emitter and the collector is shortened, the carrier travel time between the emitter and the collector is short, the current when conducting is large, and the conversion is easy. The conductance is large, the speed can be easily increased, and the driving capacity is large. At the same time, between the base and emitter, the base
The inter-collector capacitance is reduced and the operating speed is increased.
Although the BPT used in this integrated circuit is very small in size, the base resistance, which limits the operating speed of conventional BPTs, is
If the impurity density of 7, 27, and 37 is increased, there will be almost no problem. That is, the potential barrier of the base is basically controlled by the base extraction regions 4, 7, 17, 27, and 37 in a capacitive coupling manner. Capacitively coupled control is normal BPT
The height of the potential barrier is not controlled by injecting base minority carriers into the base as in the example shown in Figure 2, but rather by controlling the height of the potential barrier by the voltage applied to the base extraction electrode. In other words, in a normal BPT, when the thickness of the base is made thin as in the present invention, the resistance in the direction perpendicular to the thickness direction of the base increases, and high-speed operation is impossible due to the effect of this resistance. Because it uses capacitive coupling, it can be controlled at high speed regardless of the base resistance. In contrast to the present invention, the control of the potential barrier height by the base current of a normal BPT is resistance-coupled control. The capacitive coupling control of the present invention is similar to the height control of a potential barrier in a MOS transistor, and in principle it is also possible to use a MOS type base structure. In order to control the potential barrier capacitively in the pn junction base structure shown in Figure 1, when applying a voltage in the forward direction to the pn junction, apply a voltage below the contact potential of the pn junction. injection of minority carriers rarely occurs. Of course, even if a very small amount of minority carriers are injected, it does not matter as long as the main potential barrier control is capacitive coupling.

As shown in Figure 1, the current-voltage characteristics of a BPT, which is formed so that the base region is almost pinched off and a thin potential barrier remains between the emitter and collector, are different from the conventional BPT and the transistor by R. Zuleeg mentioned above. (US Pat. No. 3,409,812) exhibits a saturated characteristic in which the collector current is almost constant above a certain collector voltage, whereas it exhibits an unsaturated characteristic in which the collector current gradually increases as the collector voltage increases. The thickness of the potential barrier layer is determined by the value of the current flowing through the load when it is in a conductive state, and when a sufficiently large current is flowing through the load, for example
When driving a TTL (Transistor Transistor Logic) gate, it must be sufficiently thin and set close to the emitter region. Although FIG. 1 shows the case where the n ^- high resistance region exists on the collector side, it is of course possible for the n ⁺ region to be in direct contact with the base.

Also, in Fig. 1, n ⁺ areas 7, 17, 27, 37,
Although n region 8 is in direct contact with p region 9, n ^-
Area 2 to 7, 17, 27, 37 and 9 and 8 and 9
You can put it in between.

Although FIG. 1 shows an AND gate with three inputs and two outputs, it goes without saying that the number of inputs and the number of outputs may be increased or decreased as necessary.

Of course, the BPT used in the present invention described so far is not limited to these structures. It is sufficient if the base region is configured so that it is almost or completely pinched off in the main active region, leaving a thin potential barrier layer. It goes without saying that the conductivity type of the conventional one may be completely reversed.

Although the present invention relates to EFL, BPT, which is a component of the present invention, can be used with other logic gates such as ECL (Emitter Coupled Logic) and NTL (Non
Threshold Logic), DTL (Diode Tranistor
Logic), RTL (Resistor Transistor Logic),
When used in TTL (Transistor Tranistor Logic), etc., it is possible to obtain a semiconductor integrated circuit that can operate at high speed due to the small minority carrier accumulation effect and small capacitance between electrodes.

Figure 2 is an example of a basic logic configuration using the above-mentioned BPT in a circuit equivalent to EFL in the circuit display of Figure 1.
A 3-input AND gate is configured. The electrodes 71, 72, 73 in Fig. 1 are the pnp-BPT in Fig. 2.
correspond to base electrodes A, B, and C, respectively.
AND gate operation is possible even without npn-BPT.

The circuits shown in FIGS. 1 and 2 have a small interelectrode capacitance, a small minority carrier accumulation effect, a current-voltage characteristic that deviates from the saturation type, an input impedance higher than that of the conventional BPT, and a faster operating speed.
If these circuits are combined appropriately depending on the design conditions,
All desired operations can be performed. Furthermore, since the BPT has excellent high frequency characteristics, it goes without saying that it can be applied to various analog signal processing devices including integrated analog operational amplifiers.

A semiconductor integrated circuit using the structure provided by the present invention can be manufactured by conventionally well-known crystal growth techniques, diffusion techniques, ion implantation techniques, microfabrication techniques, and the like. Ion implantation technology is particularly effective when controlling the base region with good precision.

The EFL using the BPT, in which the base region is configured to be almost pinched off in the manual operation region, is based on conventional resistance-coupled potential barrier control using minority carrier injection from the base.
Unlike EFL, it operates by performing capacitive coupling potential barrier control using the voltage applied to the base, so there is little minority carrier accumulation effect, the capacitance between each electrode is small, and it does not include the state in which carriers diffuse through the base region. In addition, it is easy to shorten the channel length between the emitter and collector, the carrier travel time is short, the frequency characteristics are good, high speed operation is possible, and the drive capacity is large and the number of fan outs is large. Its industrial value is extremely high.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a structural example of an EFLAND gate using BPT whose base region is almost in a pinch-off state, and FIG. 2 is a diagram showing a circuit representation of FIG. 1.

Claims (1)

[Claims] 1 first conductivity type first semiconductor regions 9, 9';
A second semiconductor region 2 of a second conductivity type with a low impurity density formed above the first semiconductor region, and a third semiconductor region 2 of a first conductivity type with a high impurity density formed above the second semiconductor region. the third semiconductor region 6;
at least two or more fourth semiconductors of a second conductivity type with high impurity density, which are adjacent to the semiconductor region of the second semiconductor region and are formed deeper from the surface of the second semiconductor region than the third semiconductor region; Area 7, 17, 27, 3
7 and the fourth semiconductor region at the bottom of the third semiconductor region.
A fifth semiconductor region 8 having a second conductivity type impurity density of 10 ¹² to 10 ¹⁶ cm ^-3 formed adjacent to the semiconductor region 8
and at least two or more independent input signal electrodes 71 formed on the fourth semiconductor region,
72, 73, a second conductivity type high impurity density sixth semiconductor region 1 formed in a part of the upper part of the first semiconductor region, and a second semiconductor region 1 formed in the upper part of the sixth semiconductor region. seventh semiconductor regions 13 and 23 of high impurity density of conductivity type; and an eighth semiconductor of high impurity density of first conductivity type formed adjacent to the seventh semiconductor region and deeper than the seventh semiconductor region; Area 4
and a ninth semiconductor region 51 having a first conductivity type impurity density of 10 ¹² to 10 ¹⁶ cm ^-3 formed at the bottom of the seventh semiconductor region adjacent to the eighth semiconductor region,
52, the output signal electrodes 31 and 32 formed on the upper part of the seventh semiconductor region, and the third semiconductor region and the eighth semiconductor region are connected, and both are connected to a power supply via a resistor Rc. The first wiring layer 6'
a tenth semiconductor region 1' of a second conductivity type with high impurity density formed above the sixth semiconductor region and adjacent to the sixth semiconductor region; A second wiring layer 18 formed and connected to the power supply, and an isolation region 11 formed between the fourth semiconductor region and the eighth semiconductor region, and The thickness and impurity density of the fifth and ninth semiconductor regions are set such that the ninth semiconductor region becomes almost a depletion layer, leaving a thin neutral region due to the diffusion potential generated at the contact portions with the semiconductor regions above and below it. A semiconductor integrated circuit characterized in that the height of the potential barrier selected and formed in the thin neutral region is controlled in a capacitive coupling manner by voltages applied to the fourth and eighth semiconductor regions.