JPH0368567B2 - - Google Patents
Info
- Publication number
- JPH0368567B2 JPH0368567B2 JP60105515A JP10551585A JPH0368567B2 JP H0368567 B2 JPH0368567 B2 JP H0368567B2 JP 60105515 A JP60105515 A JP 60105515A JP 10551585 A JP10551585 A JP 10551585A JP H0368567 B2 JPH0368567 B2 JP H0368567B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- mis
- bistable circuit
- source
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000004913 activation Effects 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 5
- 230000007257 malfunction Effects 0.000 description 4
- 230000003213 activating effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
Landscapes
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はMISトランジスタを用いて構成される
双安定回路を含むMIS回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MIS circuit device including a bistable circuit configured using MIS transistors.
従来、双安定回路においては、二つの結合回路
は直流結合であつて、安定状態は二つある。一方
の安定状態を定める入力が与えられると、次に他
方の安定状態を定める入力が与えられるまでその
状態を保持する。二つの安定状態をそれぞれ２進
情報０，１に対応することができる。この故に、
デイジタル量を扱う回路に双安定回路が多く用い
られるようになつてきた。
Conventionally, in a bistable circuit, two coupled circuits are DC coupled, and there are two stable states. When an input that defines one stable state is given, that state is maintained until the next input that defines the other stable state is given. Two stable states can correspond to binary information 0 and 1, respectively. For this reason,
Bistable circuits are increasingly being used in circuits that handle digital quantities.
双安定回路を含むMIS回路装置において、双安
定回路の入力がこの双安定回路を活性化する場
合、この入力が入いるタイミングによつてこの双
安定回路の出力が、中間電位点に留り、この双安
定回路の次段の回路に誤動作を引き起すという欠
点がある。
In an MIS circuit device that includes a bistable circuit, when the input of the bistable circuit activates this bistable circuit, the output of this bistable circuit remains at the intermediate potential point depending on the timing of this input, and This bistable circuit has the disadvantage that it causes malfunction in the circuit at the next stage.
本発明の目的は、双安定回路の入力が、この
MIS双安定回路を活性化する信号に対して、非同
期に入力される場合においても、このMIS双安定
回路の次段に誤動作を引起させないMIS回路装置
を提供することにある。 The object of the present invention is that the input of the bistable circuit is
An object of the present invention is to provide an MIS circuit device that does not cause malfunction in the next stage of the MIS bistable circuit even when it is input asynchronously to a signal for activating the MIS bistable circuit.
本発明のMIS回路装置は、双安定回路と、イン
バータと、該インバータの入力端と第１の電位供
給端との間にソースとドレインが接続され前記双
安定回路の第１の出力にゲートが接続する第１の
MISトランジスタと、前記インバータの入力端と
第２の電位供給端との間にソースとドレインとが
接続され前記双安定回路の第２の出力端にゲート
が接続する第２のMISトランジスタと、前記双安
定回路の第２の出力端にドレイン（またはソー
ス）が接続され前記インバータの出力端にゲート
が接続される第３のMISトランジスタと、該第３
のMISトランジタのソース（またはドレイン）と
前記第１の電位供給端との間にドレインとソース
とが接続されゲートが次段の回路の活性化信号入
力端に接続する第４のMISトランジスタを含んで
構成される。
The MIS circuit device of the present invention includes a bistable circuit, an inverter, a source and a drain connected between an input terminal of the inverter and a first potential supply terminal, and a gate connected to the first output of the bistable circuit. the first to connect
a second MIS transistor having a source and a drain connected between an input end of the inverter and a second potential supply end and a gate connected to a second output end of the bistable circuit; a third MIS transistor whose drain (or source) is connected to the second output terminal of the bistable circuit and whose gate is connected to the output terminal of the inverter;
a fourth MIS transistor whose drain and source are connected between the source (or drain) of the MIS transistor and the first potential supply terminal, and whose gate is connected to the activation signal input terminal of the next stage circuit. Consists of.
次に、本発明の実施例について図面を参照して
説明する。
Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の回路図である。こ
の実施例は、双安定回路１と、インバータINV
と、このインバータINVの入力端（節点Ｎ）と
第１の電位供給端Vssとの間にソースとドレイン
が接続され双安定回路１の第１の出力端OUT1に
ゲートが接続する第１のMISトランジスタQ1と、
インバータINVの入力端と第22の電位供給端VDD
との間にソースとドレインとが接続され双安定回
路１の第２の出力端OUT2にゲートが接続する第
２のMISトランジスタQ2と、双安定回路１の第
２の出力端OUT2にドレイン（またはソース）が
接続されインバータINVの出力端にゲートが接
続される第３のMISトランジスタQ3と、この第
３のMISトランジスタQ3のソース（またはドレ
イン）と第１の電位供給端Vssとの間にドレイン
とソースとが接続されゲートが次段の回路２の活
性化信号F2の入力端に接続する第４のMISトラ
ンジスタQ4とを含んで構成される。 FIG. 1 is a circuit diagram of an embodiment of the present invention. This embodiment consists of a bistable circuit 1 and an inverter INV.
and a first inverter whose source and drain are connected between the input end (node N) of this inverter INV and the first potential supply end Vss, and whose gate is connected to the first output end OUT 1 of the bistable circuit 1. MIS transistor Q1 ,
Input terminal of inverter INV and 22nd potential supply terminal V DD
a second MIS transistor Q 2 whose source and drain are connected between and whose gate is connected to the second output terminal OUT 2 of the bistable circuit 1 and to the second output terminal OUT 2 of the bistable circuit 1 ; A third MIS transistor Q 3 whose drain (or source) is connected and whose gate is connected to the output terminal of the inverter INV, and the source (or drain) of this third MIS transistor Q 3 and the first potential supply terminal V ss , and a fourth MIS transistor Q 4 whose drain and source are connected to the input terminal of the activation signal F 2 of the circuit 2 at the next stage, and whose gate is connected to the input terminal of the activation signal F 2 of the circuit 2 at the next stage.
尚、次段の回路２として、この実施例では双安
定回路を用いたが、これは双安定回路に限定され
ず、ラツチ回路，インバータ，フリツプフロツプ
等の回路であつても良い。 In this embodiment, a bistable circuit is used as the next stage circuit 2, but this is not limited to a bistable circuit, and may be a latch circuit, an inverter, a flip-flop, or other circuits.
次に、この実施例の動作について説明する。 Next, the operation of this embodiment will be explained.
第２図は第１図に示す実施例の動作時における
信号タイミング図である。 FIG. 2 is a signal timing diagram during operation of the embodiment shown in FIG.
Ｆ１は双安定回路１の活性化信号，Ｆ２は次段
の回路２の活性化信号，Ａ，Ｂ，Ｃはデータ信号
であつて、信号Ａは活性化信号Ｆ１とは非同期に
入力される。信号ＢとＣとは互いに反転か、また
はどちらも共に論理“０”の信号である。この実
施例では、互いに反転関係の信号とした。 F1 is an activation signal for the bistable circuit 1, F2 is an activation signal for the next stage circuit 2, A, B, and C are data signals, and the signal A is input asynchronously with the activation signal F1. Signals B and C are mutually inverted or both are logic "0" signals. In this embodiment, the signals are inverted to each other.
第２図に示すように、活性化信号F1，データ
信号Ａ，Ｂ，Ｃが入力されると、双安定回路１の
出力端OUT1，OUT2における出力信号は高レベ
ルと低レベルの中間の電位点となる。このよう
に、双安定回路１の出力が中間電位点に留る状態
であつても、出力端２の中間電位を節点Ｎに対し
て、Ｎチヤネル型MISトランジスタQ2がレベル
シフトを行い、次段の回路２が活性状態となる
時、次段の回路２を活性化させる信号F2と節点
Ｎを入力とするインバータINVの出力により、
Ｎチヤネル型MISトランジスタQ3とQ4がそれぞ
れ導通状態になり、双安定回路１の第２の出力端
OUT2の電位をVssに引き下げる。次段の回路２
には出力端OUT1と節点Ｎが接続されており、次
段の回路２は誤動作を起さない。 As shown in FIG. 2, when the activation signal F 1 and data signals A, B, and C are input, the output signals at the output terminals OUT 1 and OUT 2 of the bistable circuit 1 are intermediate between the high level and the low level. becomes the potential point. In this way, even if the output of the bistable circuit 1 remains at the intermediate potential point, the N-channel MIS transistor Q 2 level-shifts the intermediate potential of the output terminal 2 with respect to the node N, and the next When the circuit 2 of the stage becomes active, the signal F2 that activates the circuit 2 of the next stage and the output of the inverter INV whose input is the node N,
N-channel MIS transistors Q 3 and Q 4 become conductive, respectively, and the second output terminal of bistable circuit 1
Lower the potential of OUT 2 to V ss . Next stage circuit 2
The output terminal OUT 1 and the node N are connected to each other, so that the next stage circuit 2 does not malfunction.
以上説明したように、本発明によれば、双安定
回路の入力が、この双安定回路を活性化する信号
に対して非同期に入力される場合においても、こ
の双安定回路の次段の回路に誤動作を引起さない
双安定回路を含んだMIS回路装置が得られる。
As explained above, according to the present invention, even when the input of a bistable circuit is input asynchronously to the signal that activates this bistable circuit, the circuit at the next stage of this bistable circuit An MIS circuit device including a bistable circuit that does not cause malfunction can be obtained.
第１図は本発明の一実施例を示す回路図、第２
図は第１図に示す実施例の動作時における信号の
タイミング図である。
１……双安定回路、２……次段の回路、Ａ，
Ｂ，Ｃ……データ信号、F1，F2……活性化信号、
INV……インバータ、Ｎ……節点、OUT1，
OUT2……双安定回路の出力端、Q1〜Q4……
MISトランジスタ。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
This figure is a timing diagram of signals during operation of the embodiment shown in FIG. 1. 1...Bistable circuit, 2...Next stage circuit, A,
B, C...data signal, F1 , F2 ...activation signal,
INV...Inverter, N...Node, OUT 1 ,
OUT 2 ... Output terminal of bistable circuit, Q 1 to Q 4 ...
MIS transistor.
Claims (1)
の入力端と第１の電位供給端との間にソースとド
レインが接続され前記双安定回路の第１の出力端
にゲートが接続する第１のMISトランジスタと、
前記インバータの入力端と第２の電位供給端との
間にソースとドレインとが接続され前記双安定回
路の第２の出力端にゲートが接続する第２のMIS
トランジスタと、前記双安定回路の第２の出力端
にドレイン（またはソース）が接続され前記イン
バータの出力端にゲートが接続される第３のMIS
トランジスタと、該第３のMISトランジスタのソ
ース（またはドレイン）と前記第１の電位供給端
との間にドレインとソースとが接続されゲートが
次段の回路の活性化信号入力端に接続する第４の
MISトランジスタを含むことを特徴とするMIS回
路装置。1 a bistable circuit, an inverter, a first MIS whose source and drain are connected between the input terminal of the inverter and a first potential supply terminal, and whose gate is connected to the first output terminal of the bistable circuit; transistor and
a second MIS having a source and a drain connected between an input end of the inverter and a second potential supply end, and a gate connected to a second output end of the bistable circuit;
a transistor; a third MIS whose drain (or source) is connected to the second output terminal of the bistable circuit and whose gate is connected to the output terminal of the inverter;
a transistor, a third MIS transistor whose drain and source are connected between the source (or drain) of the third MIS transistor and the first potential supply end, and whose gate is connected to the activation signal input end of the next stage circuit; 4's
An MIS circuit device characterized by including an MIS transistor.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60105515A JPS61263308A (en) | 1985-05-17 | 1985-05-17 | Mis circuit device |
| US06/864,652 US4771187A (en) | 1985-05-17 | 1986-05-19 | Bistable circuit |
| EP86106808A EP0203491B1 (en) | 1985-05-17 | 1986-05-20 | Bistable circuit |
| DE86106808T DE3689291D1 (en) | 1985-05-17 | 1986-05-20 | Bistable circuit. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60105515A JPS61263308A (en) | 1985-05-17 | 1985-05-17 | Mis circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61263308A JPS61263308A (en) | 1986-11-21 |
| JPH0368567B2 true JPH0368567B2 (en) | 1991-10-29 |
Family
ID=14409735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60105515A Granted JPS61263308A (en) | 1985-05-17 | 1985-05-17 | Mis circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61263308A (en) |
-
1985
- 1985-05-17 JP JP60105515A patent/JPS61263308A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61263308A (en) | 1986-11-21 |
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