JPH0369207A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase dielectric strength for a surge voltage from an external part by providing a first transistor with first channel width to be connected between a power supply terminal and an output terminal and to input a signal from an internal circuit to a gate, second transistor with the second channel width narrower than the first channel width to be connected between a ground terminal and the output terminal, and third transistor with the third channel width. CONSTITUTION:The first transistor T1 with the first channel width is provided to be connected between the power supply terminal (power supply voltage VDD) and the output terminal TM0, and to input the signal from the internal circuit to the gate, and the second transistor T2 with the second channel width narrower than the first channel width is provided to be connected between the ground terminal and output terminal TM0, and to input the signal from the internal circuit to the gate. In order to increase the yield strength of the second transistor T2 to the surge voltage, the third transistor T3, which gate is grounded, is provided parallelly with the second transistor T2 so that the sum of the channel width for this third transistor T3 and the channel width for the second transistor can be equal with the channel width of the first transistor T1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an output stage transistor for outputting data and the like.

[Conventional technology]

Conventionally, this type of semiconductor device has a power supply terminal (power supply voltage VDD) and an output terminal T, as shown in FIG.
M includes a first transistor T1 connected between the interlayers and a second transistor T2 connected between the ground terminal and the output terminal TM, and outputs a signal from an internal circuit (not shown) to the output terminal TM. .

The configuration includes an output stage circuit 1 that transmits information to the terminal.

In the transistors TI and T2 of the output stage circuit 1, when the channel widths of the transistor T1 on the power supply terminal (VDD) side and the transistor T2 on the ground terminal side are equal, the voltage between nodes A and B of the transistor Tl is . , 1 and node C-D of transistor T2. . Due to the difference in
Construction of each transistor T1 and T2. The svns characteristic is the curve CV1. in FIG. Shows differences like CV2.

Therefore, the channel width of the transistor Tl is designed to be approximately three times that of the transistor T2, and the IDS
Efforts have been made to eliminate differences in VD8 characteristics.

[Problem to be solved by the invention]

In the conventional semiconductor device described above, the channel width of the transistor T2 is narrower than the channel width of the transistor T1, so the current capability of the transistor T2 is inferior, and therefore, there is no external influence on these transistors TI and T2. When a high surge voltage is applied, the transistor T
The disadvantage of transistor T2 is that it is destroyed at a relatively low voltage compared to transistor T1.

An object of the present invention is to provide a semiconductor device that can increase its resistance to surge voltage.

[Means to solve the problem]

Suto's indirect I! a first transistor having a first channel width whose gate inputs the signal from the internal circuit; and a first transistor connected between the ground terminal and the output terminal and whose gate inputs the signal from the internal circuit; an output stage circuit comprising a second transistor having a second channel width narrower than the first channel width and transmitting a signal from the internal circuit to the output terminal; and between the ground terminal and the output terminal. and the gate thereof is connected to the ground terminal, and the sum of the second channel width of the second transistor is connected to the and the first transistor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

A first transistor T1 having a first channel width that inputs a signal from a circuit (not shown), and a first transistor T1 connected between a ground terminal and an output terminal TM and whose gate inputs a signal from the internal circuit. an output stage circuit 1 comprising a second transistor T2 having a second channel width narrower than the channel width of the first transistor T2 and transmitting a signal from the internal circuit to the output terminal TM; The sum of the second channel width of the second transistor T2 is connected to the first channel of the first transistor Tl, and the sum of the second channel width of the second transistor T2 is The first transistor T3 is configured to include the first transistor T3.

Normally, the channel width of the first transistor Tl is designed to be about three times the channel width of the second transistor T2, so if only the output stage circuit 1 is used, the current capacity against high surge voltage from the outside is Compared to the first transistor T1, the second transistor T2 has a voltage of about 173, and has a lower resistance to surge voltage.

Therefore, in the present invention, a third transistor T3 whose gate is grounded is provided in parallel with the second transistor T2 in order to increase the withstand strength of the second transistor "-T/" against the surge voltage. T3
The sum of the channel width of the transistor T2 and the channel width of the second transistor T2 is such that the channel connection of the first transistor Tl is made.

〔Effect of the invention〕

As explained above, in the present invention, the third transistor has a channel width such that the sum of the channel width of the second transistor of the output stage circuit is equal to the channel width of the first transistor. This has the effect of increasing resistance to external surge voltage.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of an example of a conventional semiconductor device, and FIG. 3 is a channel diagram of the first and second transistors of the semiconductor device shown in FIG. It is an ID9 Vos characteristic diagram when the widths are equal. 1...Output stage circuit, T1-T3...Transistor.

Claims (1)

[Claims] A first channel connected between the power supply terminal and the output terminal and having a first channel width for inputting a signal from the internal circuit to the gate.
a second transistor connected between a ground terminal and the output terminal and having a second channel width narrower than the first channel width, the gate of which inputs a signal from the internal circuit;
an output stage circuit comprising a transistor for transmitting a signal from the internal circuit to the output terminal; and an output stage circuit for transmitting a signal from the internal circuit to the output terminal; and a third transistor having a third channel width such that the sum of the width and the second channel width is equal to the first channel width of the first transistor.