JPH0369225A - Data part detection circuit device - Google Patents

Abstract

PURPOSE:To generate a synchronizing signal even concerning reception data, for which the number of flags is determined in advance, by detecting the flag in the reception data, generating the synchronizing signal corresponding to the number of flags, and delaying the reception data by the prescribed number of bits. CONSTITUTION:When the reception data are supplied to a shift register 1a of a detection circuit 1 and the reception data are '01111110', a pulse signal with a one-bit length at an H level is sent out. As a result, the output signal of a counter constituting a synchronizing signal generation circuit 2 is reset, and goes to a signal state at an L level synchronously with the rise of the pulse signal 10. Since the number of bits for the flag is '8' and the pulse signal with the one-bit length is generated by the detection circuit 1, a delay circuit 3 delays the reception data by 7 bits. Thus, a data part 11 of the reception data is synchronized to a synchronizing signal 12 at the H level to be sent out from the synchronizing signal generation circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data part detection circuit device used in a synchronization signal generation device in facsimile transmission.

[Prior art and its problems] In facsimile transmission, the transmitted signal is composed of data and flags, but a flag detection circuit that separates a flag that is a specific pattern from the supplied signal is Each bit is captured and compared with a preset flag pattern to separate only the flag from the signal.

However, when multiple flags are included in the above signal, the number of flags included in the signal is set in advance so that the flags are not captured as data, and the number of flag detections is counted to detect the boundary between data and flags. By doing this, data and flags were distinguished. Therefore, a synchronization signal can be generated for the supplied signal only for the above-mentioned signal for which the number of flags has been set in advance, and there is a problem that a synchronization signal cannot be generated in other cases. Ta.

The present invention has been made to solve these problems, and an object of the present invention is to provide a data portion detection circuit device that can generate a synchronizing signal for any input signal.

[Means for Solving the Problems] The present invention includes a flag detection circuit that detects a flag from received data and sends out a pulse signal of a predetermined bit length; The present invention is characterized in that it includes a synchronization signal generation circuit that sends out a signal that returns after a predetermined period of time after completion, and a delay circuit that delays received data for a period corresponding to the number of bits of the flag.

[Operation] The flag detection circuit sends out a pulse signal of a predetermined bit length by detecting a flag in the received data, and upon being supplied with the pulse signal, the synchronization signal generation circuit generates a synchronization signal. The delay circuit delays the received data for a predetermined period of time to obtain a received data signal that is synchronized with the synchronization signal.

[Embodiment] In FIG. 1 showing an embodiment of the data part detection circuit device of the present invention, a flag is detected from received data supplied by facsimile transmission, and when the flag is detected, a 1-bit length pulse signal is generated. The output side of the detection circuit l that sends out a low (L) level signal while the pulse signal is being supplied from the detection circuit l, and the flag bit is output from the time when the pulse signal is no longer supplied from the detection circuit l. High after a few minutes (H
) is connected to a synchronizing signal generating circuit 2 which sends out a level signal. The output side of the synchronization signal generation circuit 2 is connected to the other input terminal of an AND circuit 5, which is supplied with a clock signal to another input terminal, and the output side of the AND circuit 5 is connected to a D-flip-flop circuit (in the park, it is connected to a D-flip-flop circuit). It is connected to the clock terminal of 4 (denoted as FF).

Further, the delay circuit 3 is a circuit that is supplied with received data and delays the received data and sends it out only for a period obtained by subtracting 1 bit of the pulse signal sent out by the detection circuit 1 from the number of flag bits included in the received data. The output side of the delay circuit 3 is connected to the data input terminal of the D-flip-flop circuit 4. The D-flip-flop circuit 4 is the delay circuit 3
This is a circuit for transmitting a signal obtained by removing a flag from received data that includes a data portion and a flag to be transmitted.

As shown in FIG. 2, the detection circuit 1 consists of a shift register 1a that sends out 8 bit signals in parallel, and an AND circuit 1b that performs a logical operation based on the signal supplied from the shift register 1a. The data of the most significant bit and the least significant bit sent from the shift register 1a are sent to the AND circuit 1b via the inverter IC.

Therefore, the detection circuit 1 sends out an H level signal only when the received data is otttxtlO. The synchronizing signal generating circuit 2 is constituted by a 4-bit counter, and the output side of the detecting circuit 1 is connected to the reset terminal of the counter. Further, the delay circuit 3 is composed of a 7-bit shift register.

The operation of the data portion detection circuit configured as described above will be explained below with reference to FIG.

When received data as shown in FIG. 3A is supplied to the shift register 1a of the detection circuit 1, when the received data is 01111110 as described above, the detection circuit 1 outputs 1 bit as shown in FIG. Long H level pulse signal 10
Send out. By sending out the pulse signal 10 from the detection circuit 1, the output signal of the counter that constitutes the synchronization signal generation circuit 2 is reset, and as shown in Figure 3, it goes to L level in synchronization with the rise of the pulse signal 10. The signal state is as follows. The synchronization signal generation circuit 2 uses a 4-bit counter and uses the output of the 4th bit as the synchronization signal, so it keeps the synchronization signal at L level for 8 bits by counting the pulses of the received data. Keep it. Also, since there is a flag every 8 bits while the flags are continuous, a signal is supplied from the detection circuit 1 and the output signal of the synchronization signal generation circuit 2 is reset, so the synchronization signal is at L level. After flag detection is completed and 7 bits of received data are counted, the synchronization signal is changed to H level.

On the other hand, the delay circuit 3 delays the received data by 7 bits since the flag has 8 bits and the detection circuit 1 generates a 1-bit long pulse signal. Therefore, as shown in Figure 3, the data section 11 of the received data is synchronized with the H level synchronization signal 12 sent from the synchronization signal generation circuit 2, as shown in Figure 3.

Further, when the signal sent out from the synchronization signal generation circuit 2 and the clock signal (referred to as CLK in the park) are both at H level, the AND circuit 5 sends out an H level signal. D-
The D-flip-flop circuit 4 transmits the signal supplied to the data input terminal when the H-level signal is supplied from the AND circuit 5.
The signal sent out is a signal containing only the data portion of the received data except for the flag.

In the above-described embodiment, the case where the number of bits constituting the flag is 8 bits has been described, but the present invention is not limited to this.

As described above, according to the data part detection circuit of this embodiment, even if there are multiple flags in the received data and those flags are consecutive, it is possible to generate a synchronization signal regardless of the number of consecutive flags. can.

[Effects of the Invention] As detailed above, according to the present invention, flags are detected from received data, a synchronization signal is generated according to the number of flags, and the received data is delayed by a predetermined number of bits. Therefore, a synchronization signal can be generated even for received data for which the number of flags is not determined in advance.

[Brief explanation of drawings]

1 and 2 are block diagrams showing the configuration of an embodiment of the data portion detection circuit device of the present invention, and FIG. 3 is a time chart showing the operation of the data portion detection circuit device of the present invention. ■...Detection circuit, 2...Synchronization signal generation circuit, 3...
・Delay circuit.

Claims (1)

[Claims] (1) A flag detection circuit that detects a flag from received data and sends out a pulse signal of a predetermined bit length; and a signal that is reset by the pulse signal sent by the flag detection circuit and returns after a predetermined period of time from the end of the flag. What is claimed is: 1. A data part detection circuit device comprising: a synchronization signal generation circuit that delays received data for a period corresponding to the number of bits of a flag;