JPH0369969U - - Google Patents
Info
- Publication number
- JPH0369969U JPH0369969U JP1990036522U JP3652290U JPH0369969U JP H0369969 U JPH0369969 U JP H0369969U JP 1990036522 U JP1990036522 U JP 1990036522U JP 3652290 U JP3652290 U JP 3652290U JP H0369969 U JPH0369969 U JP H0369969U
- Authority
- JP
- Japan
- Prior art keywords
- synchronization
- pulse
- output
- signal
- generating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Synchronizing For Television (AREA)
Description
第１図は本考案に基づくパルス幅による同期検
出回路の回路図、第２図は第１図に図示された回
路の各部分に対する動作波形図である。
Ｇ１……論理積素子、１０……第１検査手段、
２０……第２検査手段、３０……出力安定化手段
、１１〜１３，２１，２２……第１〜４カウンタ
、１４……遅延素子、１５……単安定マルチバイ
ブレータ、Ｃ１……コンデンサ、２１……反転素
子、Ｑ１〜Ｑ３……トランジスタ、Ｒ１，Ｒ２…
…抵抗。
FIG. 1 is a circuit diagram of a synchronization detection circuit based on pulse width according to the present invention, and FIG. 2 is an operational waveform diagram for each part of the circuit shown in FIG. G 1 ... logical product element, 10 ... first inspection means,
20... Second inspection means, 30... Output stabilizing means, 11 to 13, 21, 22... First to fourth counters, 14... Delay element, 15... Monostable multivibrator, C1 ... Capacitor , 21...inverting element, Q1 to Q3 ...transistor, R1 , R2 ...
…resistance.
Claims (1)
て、 同期測定用パルス列を発生するパルス発生手段
と、 受信された同期信号によつて同期パルス期間の
うちに上記パルス発生手段から供給される上記測
定用パルス列を出力するゲート素子と、 受信された同期信号の同期パルス期間のうちに
上記ゲート素子から供給されるパルス列のパルス
数によつて同期信号であるかを判断する第１検査
手段と、 上記第１検査手段の出力によつて作動されて受
信された同期信号の同期パルスの幅期間のうちに
上記ゲート素子の出力パルス列のパルス数を検査
して同期信号であるかを判断する第２検査手段と
、 上記第２検査手段の出力によつて安定された論
理状態の同期検出信号を出力するための出力安定
化手段とを含むことを特徴とするパルス幅による
同期検出回路。 (2) 上記第１検査手段が上記ゲート素子の出力
パルス列をカウントして第１所定数となるときパ
ルス形態の第１同期感知信号を発生する第１カウ
ンテイング手段と、 上記第１カウンテイング手段の出力である第１
同期感知信号によつて次の同期パルス期間を充分
に占有することができる動作制御用パルスを発生
する波形整形手段とを含むことを特徴とする請求
項第１項記載のパルス幅による同期検出回路。 (3) 上記波形整形手段が上記第１カウンテイン
グ手段の出力である第１同期感知信号を次の同期
パルスの開始部分まで遅延させる遅延手段と、 上記遅延手段の出力によつて次の同期パルスの
開始部分より終了部分まで期間を充分に占有し得
るパルス幅の動作制御用パルスを発生する単安定
マルチバイブレータとを含むことを特徴とする請
求項第２項記載のパルス幅による同期検出回路。 (4) 上記第２検出手段が上記波形整形手段の出
力である動作制御用パルスによつて上記ゲート素
子の出力をサンプリングするためのゲート手段と
、 上記ゲート手段の出力パルス列をカウントして
第２所定数となるときパルス形態の第２同期感知
信号を発生して上記出力安定化手段に供給する第
２カウンテイング手段とを含むことを特徴とする
請求項第２項記載のパルス幅による同期検出回路
。 (5) 上記第２所定数は上記第１所定数より異な
る値をもつように設定することを特徴とする請求
項第４項記載のパルス幅による同期検出回路。[Claims for Utility Model Registration] (1) A video receiving device equipped with synchronization separation means, comprising pulse generation means for generating a pulse train for synchronization measurement, and a pulse train that generates the pulse train during a synchronization pulse period by a received synchronization signal. A gate element outputs the measurement pulse train supplied from the generating means, and determines whether the received synchronization signal is a synchronization signal based on the number of pulses of the pulse train supplied from the gate element during the synchronization pulse period of the received synchronization signal. and a first testing means operated by the output of the first testing means to test the number of pulses of the output pulse train of the gate element within the width period of the synchronizing pulse of the received synchronizing signal to determine whether the synchronizing signal is correct. and output stabilizing means for outputting a synchronization detection signal in a logic state stabilized by the output of the second testing means. Synchronous detection circuit. (2) a first counting means for generating a first synchronization sensing signal in the form of a pulse when the first test means counts the output pulse train of the gate element and reaches a first predetermined number; and the first counting means The first output is the output of
2. The pulse width synchronization detection circuit according to claim 1, further comprising waveform shaping means for generating an operation control pulse that can sufficiently occupy the next synchronization pulse period by the synchronization sensing signal. . (3) delay means for causing the waveform shaping means to delay the first synchronization sensing signal, which is the output of the first counting means, until the start of the next synchronization pulse; 3. The synchronization detection circuit based on a pulse width according to claim 2, further comprising a monostable multivibrator that generates an operation control pulse having a pulse width that can sufficiently occupy a period from the start to the end of the pulse width. (4) gate means for the second detection means to sample the output of the gate element using the operation control pulse output from the waveform shaping means; 3. The synchronization detection method according to claim 2, further comprising a second counting means for generating a second synchronization sensing signal in the form of a pulse when a predetermined number is reached and supplying the second synchronization sensing signal to the output stabilizing means. circuit. (5) The pulse width synchronization detection circuit according to claim 4, wherein the second predetermined number is set to have a value different from the first predetermined number.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1989-16804 | 1989-11-14 | ||
| KR2019890016804U KR920008249Y1 (en) | 1989-11-14 | 1989-11-14 | Synchronous Detection Circuit by Pulse Width |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0369969U true JPH0369969U (en) | 1991-07-12 |
| JPH067629Y2 JPH067629Y2 (en) | 1994-02-23 |
Family
ID=19291821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990036522U Expired - Lifetime JPH067629Y2 (en) | 1989-11-14 | 1990-04-04 | Sync detection circuit by pulse width |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH067629Y2 (en) |
| KR (1) | KR920008249Y1 (en) |
| GB (1) | GB2238443B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180082259A (en) * | 2017-01-10 | 2018-07-18 | 최남열 | Trowel for plasterer |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| MY108249A (en) * | 1991-12-13 | 1996-08-30 | Thomson Consumer Electronics Inc | A detector circuit for use in a vcr |
-
1989
- 1989-11-14 KR KR2019890016804U patent/KR920008249Y1/en not_active Expired
-
1990
- 1990-03-29 GB GB9007068A patent/GB2238443B/en not_active Expired - Fee Related
- 1990-04-04 JP JP1990036522U patent/JPH067629Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180082259A (en) * | 2017-01-10 | 2018-07-18 | 최남열 | Trowel for plasterer |
Also Published As
| Publication number | Publication date |
|---|---|
| KR920008249Y1 (en) | 1992-11-14 |
| GB9007068D0 (en) | 1990-05-30 |
| GB2238443B (en) | 1994-06-22 |
| GB2238443A (en) | 1991-05-29 |
| KR910010262U (en) | 1991-06-29 |
| JPH067629Y2 (en) | 1994-02-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |