JPH0370235B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a generator assigner type electronic musical instrument, and in particular, when a plurality of musical tone generation channels select the same note name, the present invention is designed to maintain a constant phase relationship of musical tone signals output from the plurality of musical tone generation channels. Regarding electronic musical instruments. A generator assigner type electronic musical instrument has a number of musical tone generation channels that can generate musical tone signals corresponding to all keys, but is smaller than the number of usable keys, and can generate musical tone signals from vacant keys by pressing the keys. It selects a channel and generates a musical tone signal corresponding to a key press. In such a generator assigner type electronic musical instrument, pressing a key selects an appropriate vacant channel of the musical tone generator of multiple channels, for example.
Channel i is selected and a musical tone signal corresponding to the key depression is generated. After that, when a key in an octave relationship (for example, one octave lower) with the musical tone signal generated in channel i is pressed and assigned to channel (i+1) to generate a musical tone signal, channel (i+
The sound generation start timing at which the musical tone signal is generated from 1) is operated at a timing that is unrelated to the musical tone signal generated in channel i. Therefore, when the phase of the fundamental wave component of the musical tone signal being generated in channel i and the phase of the second harmonic component of the musical tone signal to be generated in channel (i+1) are in opposite phase, channel (i+1) If the sounding of musical tone signals is started from , cancellation will occur between the musical tone signals and a specific pitch will not be generated. In addition, in electronic musical instruments with a two-level keyboard (upper and lower keyboards), the same note name and the same octave may be set for multiple channels, and the phase relationship of the musical tone signals generated between multiple channels may change. Depending on the timing, the phase will be opposite in the worst case. In such a state, the musical tone signals generated from the plurality of channels cancel each other out, and no musical tone signal is generated even if a key is pressed. The present invention provides a first memory that stores musical tone generation data at the operating timing of a generator assigner, and stores the contents stored in the first memory using an internal clock generated inside a musical tone generation channel. To provide an electronic musical instrument in which phase cancellation can be quickly and reliably prevented with a simple circuit configuration by transferring the signal to the second storage device. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In the figure, 1 is a keyboard, which is composed of a plurality of key switches. 2 is a generator assigner (hereinafter abbreviated as GA section), which is published in Special Publication No. 50-33407 "Multiplexing device for selecting musical tones and voices in electronic musical instruments"
It has the same function as the generator assigner already known in the art, etc., and detects the pressed state of the keys on the keyboard 1, and selects the pressed key from one of the available musical tone generation channels. A key press signal indicating the pressed/released state of the key, note data and octave data indicating the pitch are supplied to the tone generator 7. 3 is the main clock oscillator, 4 is the initial clear signal generator (hereinafter referred to as
It is abbreviated as ICRG department. ), which generates an initialization signal for the entire system when the power is turned on. 5 is a top octave synthesizer (hereinafter T
It is abbreviated as OS department. ) takes the output signal of the main clock oscillator 3 as input and generates a one-octave scale signal corresponding to the highest range of the 12-tone scale. 6 is a timing pulse generation section (hereinafter abbreviated as TPG section);
Generates timing pulses for phase matching processing.
A musical tone generating section 7 generates a predetermined musical tone signal based on the key depression signal, note data, and octave data supplied from the GA section 2. A latch 8 stores channel selection data of a predetermined musical tone generation channel TGi assigned by the GA section 2. A decoder 9 outputs a channel selection signal for selecting a predetermined tone generating channel based on the channel selection data stored in the latch 8. Reference numeral 10 denotes a tone forming section which receives the output signal (musical tone signal) of the musical tone generating section 7 and forms a predetermined tone using a low-pass filter, a band-pass filter, etc. 11 is an amplifier, and 12 is a speaker. To simplify the explanation, the number of musical tone generating channels in the musical tone generating section 7 will be described as eight channels, that is, TG ₀ to _{TG 7} . Furthermore, in the configuration diagram shown in FIG. 1, it is assumed that the GA section 2 is composed of a microcomputer, and the output A/D has an 8-bit configuration. First, when the power supply changes from FF to N,
An initial clear pulse is generated from the ICRG section 4. Then, the GA section 2, TS section 5, TPG section 6, and tone generating section 7 are initialized. Then, select a key on keyboard 1, for example, a key switch.
When KC ₁ is pressed, the GA section 2 assigns an appropriate musical tone generation channel TGn and the GA
Musical sound generation channel selection data (hereinafter abbreviated as CH selection data) and musical sound generation data (key press signals, note data, octave data) are sent from the section 2 to the musical sound generation section 7. FIG. 2 shows the timing of data sent from the GA section 2 to the tone generating section 7. As can be seen from Fig. 2, the output A/ of the GA section 2 is
CH selection data and musical tone generation data are sent from D in a multiplexed form. During the timing when the CH selection data is being sent from the output A/D, the output ALE selects a logic low level (hereinafter abbreviated as "0") → logic high level (hereinafter abbreviated as "1") → CH selection of "0". A data write pulse (hereinafter abbreviated as CDWP signal) is sent out. Also, during the timing when musical tone generation data is being sent from the output A/D, the output WR becomes “0” →
A tone generation data write pulse (hereinafter abbreviated as TDWP signal) changing from "1" to "0" is sent out.
CDWP sent from output ALE and output WR
The signal and the TDWP signal become write signals for storing CH selection data and musical tone generation data on the musical tone generation section 7 side. When the CH selection data and musical tone generation data are transferred to the musical tone generation section 7 according to the timing relationship shown in FIG. 2, the CH selection data is first transferred to the latch 8.
It is stored at the timing when the CDWP signal changes from "1" to "0". Then, in the decoder 9, based on the CH selection data stored in the latch 8, a selection signal ("1") is sent from the output Sn to the input SEL of the tone generation channel. Table 1 shows the relationship between CH selection data and selected musical tone generation channels.

【table】

[Table] Output A/D of GA section 2 as CH selection data
The lower 3 bits of A/D0, A/D1,
I am using A/D2. After a predetermined musical tone generation channel TGn is selected, when the musical tone generation data and the TDWP signal are applied from the GA section 2 to the musical tone generating section 7, the predetermined musical tone is generated at the timing when the TDWP signal changes from "1" to "0". Tone generation data is stored in the generation channel TGi. Here, the data structure of the musical tone generation data will be explained. Table 2 shows the composition of the musical tone generation data. The upper four bits of the output A/D of the GA section 2, ie, A/D4 to A/D7, become note selection data, and Table 3 shows the relationship between note selection data and selected note names. The fourth bit, A/D3, is key N/FF data representing the N/FF state of the key switch; "1" indicates the N state, and "0" indicates the FF state. Then, the lower 3 bits, that is, A/D0 to A/
D2 becomes octave selection data. Table 4 shows the relationship between octave selection data and selected octaves.

【table】

【table】

[Table] When musical sound generation data is stored in a predetermined musical sound generation channel TGn, T
A desired highest scale signal is selected from the S section 5, and the selected scale signal is inputted to form a scale signal corresponding to the entire tone range using an octave frequency divider. After selecting a scale signal in a desired range using the octave selection data, amplitude modulation is performed based on the key N/FF data and output as a musical tone signal from the musical tone generation channel. The musical tone signals output from each musical tone generation channel are applied to the tone forming section 10 to form a desired tone. The tone formed by the tone forming section 10 is output from the speaker 12 via the amplifier 11. Thereafter, when a new key switch is pressed, a musical tone signal corresponding to the pressed key is generated from the unselected musical tone generation channel TG by the same operation as described above. Next, the phase matching operation will be explained. As mentioned above, there is a generator assigner type electronic organ system which has fewer musical tone generation channels than the number of usable keys, selects an empty tone generation channel by key press operation, and generates a musical tone signal corresponding to the key press. In this case, each musical tone generation channel is designed to generate musical tone signals corresponding to all available keys, and the frequency division state of the octave frequency divider in the musical tone generation channel is different between each musical tone generation channel. Sometimes there are. In such a situation, multiple channels, for example, musical tone generation channel TG ₀
If note selection data with the same note name is input to musical sound generation channel TG ₁ , musical sound generation channel TG ₀
The timing of inputting note selection data and the frequency division state of the octave frequency divider are different between TG 1 and TG ₁ , and if a musical tone signal is generated as is, the phase relationship of the musical tone signal will be between the two channels, and in most cases,
In the worst case, the phases of the musical tone signals of the two channels will be in opposite phases. In this case, cancellation occurs between the musical tone signals, and no musical tone signal is generated. Therefore, even when the same note name is input to multiple musical tone generation channels, the frequency division state of the octave frequency divider is made equal to prevent the above-mentioned phenomenon of phase cancellation between musical tone signals. This is called a matching operation. This operation will be described below. For example, if you set the key switch to musical sound generation channel TG ₀ ,
Assume that KC ₁ is assigned and a musical tone signal corresponding to key switch KC ₁ is generated. Then, the octave frequency division contents (phase data) of the musical sound _generation channel TG ₀ are transmitted to _{PD 1 and}
It is periodically sent from PD ₂ to the phase data bus at predetermined time slots. After that, when key switch KC ₂ , which has an octave relationship with the musical tone signal generated in musical tone generating channel TG ₀ , is assigned to musical tone generating channel TG ₁ ,
This means that the same note name is assigned to musical tone generation channels TG ₀ and TG ₁ . At this time, the octave frequency division contents of the musical tone generation channel TG ₀ superimposed on the phase data bus are transferred to the octave frequency divider of the musical tone generation channel TG ₁ at a predetermined timing by timing pulses φ ₀ to φ ₆ generated by TPG 6. Write sequentially to As a result, the octave frequency division contents of the musical tone generation channels TG ₀ and TG ₁ are equal, and the phase relationship of the musical tone signals is the same between the two channels. Then, when the writing process is completed, the octave frequency-divided contents of the musical sound generation channels TG ₀ and TG ₁ are periodically sent to the phase data bus in the same time slot by timing pulses φ ₀ to _{φ 6} from the TPG section 6. will be done. Additionally, if the octave frequency divider of musical tone generating channel TG ₀ performs count-up or count-down processing while writing phase data to musical tone generating channel TG ₁ as described above, musical tone will be generated again. It is necessary to write the octave frequency division contents of musical tone generation channel TG ₀ to channel TG ₁ . This is because the timing at which the phase data is written is unrelated to the timing at which the octave frequency divider counts up or down, so if the count up or down is performed, the phase data will be lost in the middle of writing. Mistakes occur. If a writing error occurs, the contents of the octave frequency dividers of both channels will not match, and the phase relationship of the musical tone signals may become opposite, causing cancellation of the musical tone signals. FIG. 3 shows a configuration diagram of the TPG section 6. In the figure, 13 is a 1/2 frequency divider flip-flop (hereinafter referred to as
Abbreviated as FFF. ) divides the clock signal input from the input MC by 1/2. 14 is a counter, 7
Consists of bits. 15 and 18 are NAND
Gates, 16 and 19 are D-type flip-flops (hereinafter abbreviated as DFF), 17 is an inverter, and 20 is a
It is an AND gate. When the power is turned on, input ICR is output from ICRG section 4.
A reset signal of "0"→"1"→"0" is input to the input terminal. Then, a reset pulse is applied to the input R of the FF13 and the input R of the counter 14 via the inverter 17 and NAND18.
13, the outputs Q of the counter 14 all become "0". Then, after the initial clear process is completed, input
The FF 13 and counter 14 sequentially perform count-up processing based on the clock signal from the MC. After that, when the outputs Q ₃ , Q ₅ , Q ₆ of the counter 14 become “1”, the output of the NAND 15 changes from “1” to “0”, and the timing at which the output Q of the FF 13 changes from “1” to “0” and NAND to DFF16
15 output signals are stored. Then,
The output Q of DFF16 changes from “1” to “0”.
A reset signal (“1”) is applied to the input R of the counter 14 via the NAND 18. counter 14
When "1" is applied to the input R of the counter 14, the counter 14 is reset and the outputs _Q0 to _Q6 all become "0".
When the outputs Q ₃ , Q ₅ , Q ₆ become “0”, the output of NAND15 changes from “0” to “1”, and at the timing when the output Q of FF13 changes from “1” to “0”.
The output Q of the DFF16 becomes "1" again. Then, "0" is applied to the input R of the counter 14 again, and the count-up process is restarted. DFF19 and AND20 form a 1/4 duty pulse wave. FIG. 4a shows a timing chart of timing pulses φ ₀ to _{φ 6} output from the TPG section 6. In addition, Figure b shows the types of phase data that appear periodically on the phase data bus. After the processing timing corresponding to the C note ends, the processing timing corresponds to the C# note, and so on. When the B sound ends, the C sound processing timing returns. In this way, from C note to B
Timing pulses φ ₃ to _{φ 6} manage the time-division processing timing of sound. Figure c shows the timing at which phase data within one tone is read out. Here, the octave frequency division contents are sequentially read out to time slots 1, 2, and 3. Timing pulses φ ₁ and φ ₂ manage this timing. FIG. 5 shows a specific example of the musical tone generation channel TGn. In the figure, a latch 21 stores musical tone generation data in response to the TDWP signal from the GA section 2, and is composed of 8 bits. input
D ₀ , D ₁ , and D ₂ correspond to octave selection data, input D ₃ corresponds to key N/FF data, and input D ₄ , D ₅ , D ₆ , and D ₇ correspond to note selection data. A latch 22 stores the data stored in the latch 21 in synchronization with an internal clock (a clock signal formed by a timing pulse from the TPG unit 6). (The signals (note selection data) output from outputs Q ₄ , Q ₅ , Q ₆ , and Q ₇ are assumed to be new note data.)
Reference numeral 23 denotes a note selector, which selects one of the scale signals from the TS unit 5 based on the note selection data (Q ₄ to Q ₇ ) stored in the latch 22, and its configuration is already publicly known. It is a data selector. Reference numeral 29 is a latch, which is composed of 4 bits and stores note selection data corresponding to the note name that was being sounded before the new musical tone generation data was transferred from the GA section 2. Set the data as old note data. 30 is a comparator that compares the new note data stored in the latch 22 and the old note data stored in the latch 29. If the new and old note data are the same, the output A=B. 0" is output. Expressed as a logical formula, (A=B)=(A ₀ B ₀ )+(A ₁
B ₁ ) + (A ₂ B ₂ ) + (A ₃ B ₃ ). 32 is a comparator, which compares the new note data stored in the latch 22 with the timing pulses φ ₃ , φ ₄ , φ ₅ , from the TPG unit 6;
_φ6 , and detects the phase data write/read processing timing for performing time-division processing for each note name. Expressed as a logical formula, (A=B)=(A ₀ B ₀ )+(A ₁ B ₁ )+(A ₂
B ₂ ) + (A ₃ B ₃ ). 33 is a decoder, and "1" is selected for outputs _Q0 to _Q3 in response to signals applied to inputs A and B. 34 and 35 are D-type flip-flops (hereinafter referred to as DFF), and 47 to 52 are presettable 1/2 flip-flops (hereinafter referred to as PFF).
It is abbreviated as ) constitutes an octave frequency divider.
When "1" is applied to the input P, the data applied to the input D is forcibly stored and appears at the output Q. Further, when "1" is applied to the input R, a reset operation is performed and the output Q becomes "0". Then, each time the signal applied to the input CK changes from "1" to "0", the output Q is inverted. Let the frequency of the output signal of the note selector 23 be
The relationship between the frequency of the output signal outputted from the output Q of PFF47 to PFF52 is as follows. Output Q of PFF47.../2 Output Q of PFF48.../4 Output Q of PFF49.../8 Output Q of PFF50.../16 Output Q of PFF51.../32 Output Q of PFF52.../64 63 is With the octave selector, the above PFF47
The output signal of ~PFF52 is input, and the octave selection data ( _Q0 ~
_Q2 ) is used to select a scale signal in a predetermined range. A configuration diagram of the octave selector is shown in the sixth section.
As shown in the figure. Data selectors 65 to 69 select one of the signals applied to inputs D ₁ to D ₇ by inputs A, B, and C. Output ₁ by inputs A, B, and C of octave selector 63
Table 5 shows the relationship between the scale signals appearing in ~ ₅ .

【table】

[Phase data writing process]

Then, the new note data and the timing pulses φ ₃ to _{φ 6} are compared in the comparator 32, and when the new note data and the timing pulses φ ₃ to φ ₆ become equal data, the output A=B of the comparator 32 becomes “0”.
is output. This makes it possible to determine the processing timing corresponding to the C note. Then, the output signal of NR37 is “1”,
The output signal of NR38 becomes “0” and DFF3
No. 4 is enabled to latch data by input CK.
The output signal of AND41 is influenced by timing pulse φ ₀ . The NANDs 53 to 58 are in an open state (the output signal does not change depending on the input signal), and all output signals become "1". Then, the output signals of the NANDs 59 and 60 become "0" and the NchTRs 61 and 62 become in the FF state. Further, "1" is applied to the input D of the DFF 35. <Timing pulse φ ₁ = “1”, φ ₂ = “0”> When internal clock 2 (output signal of NAND40) is generated, internal clock 2 changes from “1” to “0”.
The output Q of the DFF 35 changes from "0" to "1" at the timing of the change. DFF35 output Q
When becomes “1”, NAND25 becomes open state,
NAND31 will be dependent on internal clock1. Also, timing pulse φ ₁ = “1”, φ ₂ = “0”
This means that the output Q ₁ of the decoder 33 is “1” and the output signal of the AND 42 is the timing pulse φ ₀
It will depend on. That is, preparations for writing the phase data into the DFFs 47 and 48 are now complete. Timing pulse φ ₀ changes from “0” to “1” to “0”
When the signal changes to “1”, it is superimposed on the phase data bus and is transferred from PD ₁ and PD ₂ to inverter 4.
The phase data applied to the inputs D of the PFFs 47 and 48 via the PFFs 5 and 46 is forcibly stored. <Timing pulse φ ₁ = “0”, φ ₂ = “1”> When timing pulse φ ₁ = “0”, φ ₂ = “1”, the output Q ₂ of the decoder 33 becomes “1” and
43 will be influenced by the timing pulse φ ₀ . The phase data superimposed on the phase data bus is stored in the PFFs 49 and 50 at the timing when the timing pulse φ ₀ is “1”. <Timing pulse φ ₁ = “1”, φ ₂ = “1”> When timing pulse φ ₁ = “1”, φ ₂ = “1”, the output Q ₃ of the decoder 33 becomes “1” and
44 will be influenced by the timing pulse φ ₀ . The phase data currently superimposed on the phase data bus is stored in the PFFs 51 and 52 at the timing when the timing pulse φ ₀ is “1”. Then, the processing timing changes from C note to C# note. That is, the output signal of the comparator 32 changes from "0" to "1". <Timing pulse φ ₁ =“0”, φ ₂ =“0”> When the internal clock 1 is generated again, the internal clock 1 is applied to the input CK of the latch 29 via the NAND 31. Internal clock 1 changes from “0” to “1”
New note data is transferred to the latch 29 at the timing of the change. Then, the new note data and the old note data become equal, and the output signal of the comparator 30 becomes "0". When the output signal of the comparator 30 changes from "1" to "0", it means that the phase data writing process has been completed, and the phase data reading process becomes possible. As a result, NR3
The output signal of NR 7 becomes "0", the output signal of NR 38 becomes "1", and the DFF 34 becomes in a reset state.
AND41 becomes open, "0" is output as the output of AND41, and AND42, 43, and 44 also become open. As a result, no write pulse is applied to the inputs P of the PFFs 47 to 52. On the other hand, N
The output signal of R38 is the input of comparator 32.
Depending on the output of
It becomes possible to superimpose it on the phase data bus via 2. <Timing pulse φ ₁ = “1”, φ ₂ = “0”> Then, when internal clock 2 is generated, the output Q of DFF35 becomes “0” again at the timing when internal clock 2 changes from “1” to “0”. ” becomes. In this case, the NAND 31 is held open and the old note data is held, while the output signal of the NAND 25 is controlled by the internal clock 1, so that new tone generation data can be transferred to the latch 22. [Phase data read processing] After the phase data write process is completed, as long as the new note data does not change, the processing timing corresponding to the C note, that is, the octave frequency divider is changed every time the output signal of the comparator 32 becomes "0". The contents will be sent to the phase data bus. This is because the new note data and the old note data are equal, so the output signal of the comparator 30 is "0", and the C
At the sound processing timing, the output signal of the comparator 32 also becomes "0" and the output signal of the NR38 becomes "1".
becomes. The output signals of NANDs 53-58 are then dependent on the output signals of decoder 33 and octave frequency dividers (PFFs 47-52), ie, the outputs of the octave frequency dividers are sent to the phase data bus. This will be explained for each timing pulse state. <Timing pulse φ ₁ = “0”, φ ₂ = “0”> Since the outputs Q ₁ , Q ₂ , and Q ₃ of the decoder 33 are “0” and the NANDs 53 to 58 are in the open state, no phase data is sent out. Become. <Timing pulse φ ₁ = “1”, φ ₂ = “0”> Only the output Q ₁ of the decoder 33 becomes “1” and PFF
The output signal of 47 is NAND53, 59 and
It is sent from PD ₁ to the phase data bus via NchTR61. And the output signal of PFF48 is also NAND54,
60 and NchTR 62 from PD ₂ to the phase data bus. <Timing pulse φ ₁ = “0”, φ ₂ = “1”> Only the output Q ₂ of the decoder 33 becomes “1” and PFF
49 output signal is NAND55,59 and
It is sent from PD ₁ to the phase data bus via NchTR61. And the output signal of PFF50 is also NAND56,
60 and NchTR 62 from PD ₂ to the phase data bus. <Timing pulse φ ₁ = “1”, φ ₂ = “1”> Only the output Q ₃ of the decoder 33 becomes “1” and PFF
The output signal of 51 is NAND57, 59 and
It is sent from PD ₁ to the phase data bus via NchTR61. And the output signal of PFF52 is also NAND58,
60 and NchTR 62 from PD ₂ to the phase data bus. Thereafter, when the processing timing changes from the C sound to the C# sound, the output signal of the comparator 32 changes from "0" to "1", and the output signal of the NR 38 becomes "0". Then, the NANDs 53 to 58 become open, and the transmission of phase data ends. Thereafter, when the key switch KC2, which is in an octave relationship with the key switch _KC1 , is pressed, the unselected musical tone generation channel TG is selected and the phase data writing process as described above is performed.
As a result, the frequency division contents of the octave frequency dividers of the tone generation channels corresponding to the key switches KC ₁ and KC ₂ become equal. Then, the octave frequency divider is counted up by the same highest scale signal from the TS section 4, so that cancellation of the musical tone signal does not occur. Furthermore, the reason why musical tone generation data is stored in the latch 21 using the TDWP signal and the data stored in the latch 21 is transferred to the latch 22 using the internal clock 1 is as follows. It operates at a timing unrelated to the output signal of the TPG section 6 which determines the timing at which musical tone generation data is sent from the GA section 2 to the musical tone generation channel and the timing of the phase matching operation. If only the latch 21 is used, the new note data may change at any timing during the phase matching process. When the note selector 23 selects the scale signal from the TS section 5 due to a change in new note data, the DFF3
4 operates, and the phase matching process is performed at least twice. Further, it is necessary to take into account delays in the operation of the circuit for performing the phase matching process, and the circuit configuration becomes complicated. Furthermore, the reason why the output signal of NAND25 is applied to AND24 is that when the TDWP signal and internal clock 1 overlap, that is, when the latch operations of latch 21 and latch 22 overlap, the output signal is transferred to latch 22. This is because the musical tone generation data has a negative effect on the phase matching process, causing malfunctions. When the TDWP signal changes from “0” to “1”, NAND25 becomes open and latch 2
A clock signal is no longer input to input CK of No.2. The TDWP signal is then applied to the input of latch 21 via AND24. As described above, the present invention stores musical tone generation data in the first memory device (latch 21 in the embodiment) at the operating timing of the generator assigner, and stores the contents stored in the first memory device in the musical tone generation channel. Since the data is transferred to the second memory (latch 22 in the embodiment) using an internal clock generated internally,
Even if the operation timings of the generator assigner and phase matching processing are independent, there is no need to worry about delays in circuit operation for performing phase matching processing, the circuit configuration can be simplified, and phase matching can be done quickly and reliably. The excellent effect of processing can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a timing chart of data sent from a generator assigner, FIG. 3 is a circuit diagram of a specific example of a timing pulse generator, and FIG. 4 is a circuit diagram of a specific example of a timing pulse generator. A timing chart sent out from a timing pulse generator, FIG. 5 is a circuit diagram of a specific example of a musical tone generation channel, FIG. 6 is a circuit diagram of a specific example of an octave selector,
FIG. 7 is a timing chart of the internal clock generator. 1...keyboard, 2...generator assigner, 3
...Main oscillator, 4...Initial clear signal generator, 5...Top octave synthesizer, 6...
...timing pulse generating section, 7... musical tone generating section,
8...Latch, 9...Decoder, 21...Latch, 22...Latch, 25, 28...NAND,
24...AND.

Claims (1)

[Claims] 1. A plurality of musical sound generation channels that generate musical sounds;
An electronic musical instrument comprising a generator assigner that assigns a musical tone requested by a key switch to an appropriate vacant channel among the plurality of musical tone generating channels, wherein the musical tone generating channel is sent from the generator assigner. a first memory that stores musical tone generation data according to a write signal from the generator assigner; and an internal clock in the musical tone generation channel to transfer the contents of the first memory to a second memory. means, selecting the highest scale signal corresponding to the generated note name from the highest scale signal generation section based on the musical tone generation data stored in the second storage device, and generating each scale based on the selected highest scale signal; an octave frequency divider that generates a scale signal corresponding to the octave frequency divider; means for periodically outputting the contents of the octave frequency divider as phase information to a phase data bus in the form of time division multiplexing for each note name; and the phase data. a presetting means for inputting phase information from a bus and presetting the phase information corresponding to the generated note name into the octave frequency divider; and a phase control unit for activating the presetting means when the assigned note name is different from before being assigned. The storage device is characterized by comprising a matching circuit and an adjusting circuit that inhibits operation of the means for transferring the contents of the first memory to the second memory when the write signal and the internal clock occur simultaneously. electronic musical instruments.