JPH0370414B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application This invention relates to a CMI encoding circuit that converts a normal NRZ code signal into a CMI code signal for a transmission signal.

(b) Conventional technology CMI code is a type of 1B2B code that encodes a 1-bit data signal into 2-bit blocks, with data “0” in blocks of “01” and data “1” in the middle. A code that is encoded into blocks of "00" and "11" alternately, regardless of data "0".

A block diagram of a conventional CMI encoding circuit is shown in FIG.

In Figure 4, 4, 1, 4, 2 are input terminals, 4, 1 are input terminals for the NRZ code data signal, and 4, 2 are the input terminals for the clock signal synchronized with the NRZ code data signal. . Latch circuit 4,
3 latches data signal 4, a, and outputs signal 4, b when data is “0” and data is “1”
It is separated into signals 4 and c which are output when . The clock signals 4, d input from the input terminals 4, 2 are input to the gate circuits 4, 4 of data "0", and the signals 4, d are input to the gate circuits 4, 4 of data "0".
b opens the gate and outputs the clock signal 4.d only when the data is "0". Furthermore, the output signals 4.e of the level storage circuits 4.5 for data "1" which alternately output levels "0" and "1" each time data "1" is input are transferred to the gate circuit 4.e for data "1".
6, the gate is opened by signal 4.c, and signal 4.e is output only when the data is "1". Then, the output signal 4.f of the gate circuit 4.4 and the output signal 4.f of the gate circuit 4.6 are generated by the combining circuit 4.7.
g and generates a CMI code signal 4 h,
Output to output terminals 4 and 8.

The specific circuit shown in FIG. 4 is shown in FIG. 5, and the timing chart of each signal is shown in FIG. In FIG. 5, 5.1 is an input terminal for an NRZ code data signal, 5.2 is an input terminal for a clock signal synchronized with the NRZ code data signal, 5.3 is a flip-flop constituting a data signal latch circuit, and 5.・4
is a NOR gate forming a gate circuit for data “0”. Furthermore, 5.5 is NOT gate, 5.
6 is a NOR gate, and 5 and 7 are flip-flops, which constitute a level storage circuit for data "1". Further, 5 and 8 are NOR gates forming a gate circuit for data "1", 5 and 9 are EX-OR gates forming a synthesis circuit, and 5 and 10 are output terminals for the CMI code. In addition, 5.a~ in Figure 6
5.h indicates signals of each part in FIG.

As described above, in the conventional circuit, the gate circuit for data "0" and the gate circuit for data "1" perform CMI separately for data "0" and "1".
These are encoded, combined in the final stage, and output as a CMI code. In Figure 5, EX-
OR gates 5 and 9 are the synthesis circuits, which input signals 5 and 5, which are CMI-encoded data “0” and signals 5 and g, which are CMI-encoded data “1”, and receive CMI-encoded signals 5 and 9. Output h.

(c) Problems to be solved by the invention However, in this circuit system, the signal 5.
Since the number of gates through which f and signal 5.g pass is different, a difference in gate delay occurs between the two signals, and a glitch occurs at the position indicated by the arrow of signal 5.h in FIG. Furthermore, even if the number of gates passing through is equal, glitches occur due to differences in the temperature characteristics of each gate and waveform distortion due to increased speed. Conventionally, in order to remove this glitch, 2
The waveform is shaped using a multiplied clock, but as the speed increases, the waveform becomes distorted and the glitch width widens, so there is a drawback that bit errors occur depending on the timing of the signal and the doubled clock.

This invention was made in consideration of the above circumstances, and when encoding a data signal of an NRZ code into a CMI code, the glitch is not caused in the output signal of the CMI code, regardless of the gate delay of each signal in the circuit. The present invention provides a stable CMI encoding circuit that does not generate such waveform defects.

(d) Means for solving the problem This invention delays the NRZ code signal to
In a CMI encoding circuit that encodes into a code signal,
A clock signal generation circuit, an output inversion circuit that performs an output inversion operation when receiving a clock signal to form and output a CMI code signal, compare the NRZ code signal and the CMI code signal, and based on the result, a gate circuit that opens and closes the gate in response to the command signal and supplies a clock signal to the output inversion circuit; and a memory circuit that stores the level as a memory signal, and the determination circuit is configured such that when the NRZ code signal is 0, the CMI code signal being output is 01, and when the NRZ code signal is 1, CMI being output
A command signal is output to the gate circuit so that the code signal is inverted and becomes 00 or 11 when the NRZ code signal and the storage signal are at the same level.
This is a CMI encoding circuit.

(E) Effect The determination circuit receives, for example, the NRZ code signal.
When “0” is input, the output inverting circuit
If "1" is being output as a CMI code signal, the output is inverted; if "0" is being output, the output is maintained and in both cases the output is inverted after half a clock. Also, for example, when "1" is input as the NRZ code signal,
Only when the storage circuit and the output inversion circuit both output signals of the same level, the output of the output inversion circuit is inverted and CMI encoding is performed.
In other words, the judgment circuit is the output inverting circuit.
The CMI encoded output is fed back and compared with the input NRZ encoded signal to determine the next signal level to be output, and the output of the output inverting circuit is inverted to reach that signal level. Since the CMI code signal is formed by the inversion operation, a stable output is always obtained.

(F) Embodiments The present invention will be described in detail below based on embodiments shown in the drawings. Note that this invention is not limited to this.

FIG. 1 is a block diagram showing the configuration of the present invention. In Figure 1, 1, 1, 1, and 2 are input terminals, 1 and 1 are input terminals for the NRZ code data signal, and 1 and 2 are the input terminals for the clock signal synchronized with the NRZ code data signal. . The latch/delay circuits 1 and 3 latch the data signal and output the data signal, an inverted signal, and data delayed by a half clock. The determination circuits 1 and 4 compare the input data signals from the latch/delay circuits 1 and 3, the level held in the data "1" level storage circuits 1 and 5, and the level currently output as a CMI code. When comparing and outputting the next data signal after CMI encoding, gate circuits 1 and 6 are used only when the currently output level needs to be inverted.
Open any one of the gates 1 and 8 and output the clock signal to the output inverting circuits 1 and 9. The output inverting circuits 1 and 9 are circuits that invert the output at the rising edge of the clock signal of each of the three input signal lines, and output them as CMI code signals to the output terminals 1 and 10.
Next, the operation of the determination circuits 1 and 4 will be explained.
When data “0” is input, “01” is output as the CMI code, so if the level currently being output as the CMI code is “1”, the output is inverted and the level is set to “0” first. There must be. Therefore, the gate circuits 1 and 6 are opened, and the clock signals are output to the output inverting circuits 1 and 9 to invert the current output and set the level to "0". Also, when data "0" is input and the level output as a CMI code is "0", there is no need to invert the output, so gate circuits 1 and 6 are kept closed and the output is Avoid flipping. In either of the above cases, the level output as a CMI code must be inverted from "0" to "1" after half a clock. Therefore, gate circuits 1 and 7 are opened, and a clock signal delayed by half a clock is outputted to output inverting circuits 1 and 9 to invert the current output and set the level to "1". On the other hand, when data "1" is input, if "11" was output as the CMI code when the data was "1" before then, "00" is output, and conversely, if "00" was output, "11" is output. Output. The level storage circuit for data "1" retains the level output at the time of the previous data "1", and the judgment circuits 1 and 4 judge this and determine the level to be output next and the current CMI. The level outputted as a code is compared, and only when the output needs to be inverted, the gate circuits 1 and 8 are opened and a clock signal is output to the output inversion circuits 1 and 9 to invert the current output. Also, at this time, the output level of this CMI code is held in the level storage circuits 1 and 5 for data "1", and is output to the decision circuits 1 and 4 as a decision signal when the next data "1" is input. . As described above, the judgment circuits 1 and 4 judge the level at which to output the input data as a CMI code, and only when the level currently being output as a CMI code needs to be inverted, the gate circuit 1・It operates to output the clock signal to the output inverting circuits 1 and 9 through the circuits 6 to 1 and 8.

FIG. 2 is an electrical circuit diagram of one embodiment corresponding to the block diagram of FIG. 1, and FIG. 3 is a timing chart of each signal in FIG. 2. In Figure 2, 2.1 is
NRZ code data signal input terminal, 2.2 is
An input terminal for a clock signal synchronized with the data signal of the NRZ code; 2, 3, 2, and 4 are flip-flops that each constitute a latch/delay circuit for the data signal; 2 and 5 are flip-flops that constitute a part of the determination circuit;
OR gate, 2.6 to 2.8 are AND gates that constitute a judgment circuit and a clock signal gate circuit;
2.9 and 2.10 are AND gates and flip-flops that constitute a data "1" level storage circuit, respectively; 2.11 to 2.13 and 2.10;
14 to 2.18 are flip-flops and NAND gates that constitute the output inverting circuit, respectively;
19, 2 and 20 are EX-OR gates that constitute a circuit that outputs a clock signal and its inverted signal so that there is no difference in gate delay;
21 is a CMI code output terminal. Further, 2.a to 2.j in FIG. 3 indicate signals of each part in FIG.

Next, the operation shown in FIG. 2 will be explained.

First, the clock signal input from the input terminal 2.2 is input to the EX-OR gate 2.19, 2.20, and the clock signal 2.b from the EX-OR gate 2.19 is input to the EX-OR gate 2.2. 20 outputs a clock inversion signal. The flip-flops 2 and 3 latch the data signal 2 and a input from the input terminals 2 and 1 with the clock signal 2 and b, and output the data signal 2 and c from the output Q and the inverted signal thereof, respectively. Flip Flop 2・
4 further latches the data signal 2.c with an inverted clock signal, thereby outputting the data signal 2.d delayed by half a clock from the output Q, and the inverted signal thereof from the output. AND gates 2 and 6 input the inverted signal of data signal 2.c, the output signal of the CMI code, and the inverted clock signal, so that when the data signal 2.a is "0", the level currently output as the CMI code is When it is "1", a clock inversion signal is output (signal 2.g). AND gate 2・
7 inputs the inverted signal of the data signal 2.d delayed by half a clock and the clock signal 2.b, thereby outputting the clock signal 2.b whenever the data signal 2.d is "0" (signal 2.・h). By inputting the data signal 2.d delayed by half a clock and the clock signal 2.b, the AND gates 2.9 output a clock signal whenever the data signal 2.d is "1" (signal 2.e ). Flip-flop 2.10 latches the output signal of the CMI code with signal 2.e, thereby generating data signal 2.e.
The level of the CMI code output when d is "1" is held. EX-OR gates 2 and 5 are connected to the outputs of flip-flops 2 and 10 (signals 2 and f).
By inputting the CMI code output signal, the level previously output with data “1” and the current CMI
When the levels output as codes are equal, a level "1" is output. AND gates 2 and 8 receive data signals 2 and c, and outputs of EX-OR gates 2 and 5,
By inputting the clock inversion signal, the clock inversion signal is output when the data signal 2/c is "1" and the level previously output with data "1" and the level currently output as the CMI code are equal. (signal 2・i). The signal 2・g mentioned above,
2.h and 2.i are clock signals for inverting the output signal of the CMI code. Flip Flop 2・
At 11, 2.12, and 2.13, the internal latch signals are inverted by signals 2.g, 2.h, and 2.i, respectively. NAND gates 2.14 to 2.18 are the output Q of flip-flops 2.11 to 2.13.
If there is an even number (0 or 2) of which the level is "1", the level is "0", and if the number is an even number (1 or 3), the level "1" is set to the NAND gate 2.
Output from 18. As a result, when the latch signal of any one of the flip-flops 2.11 to 2.13 is inverted, the outputs of the NAND gates 2.18 are inverted. With the above operation, the output signal 2.j of the NAND gate 2.18 becomes the data signal 2.a.
The signal is encoded into a CMI code.

In the above-mentioned embodiment, since the clock signal and the clock inversion signal have a duty of 50%, there is a risk that the rise and fall of each of the signals 2.g to 2.i in FIG. 3 will occur almost at the same time. Although the scale of the output inversion circuit has to be increased, as shown in FIG.
7.19, if the period during which the level is "1" is shortened, the signals 7.h to 7.j will be reduced as shown in FIG.
Since the rise and fall of each signal never occur at the same time, an output inversion circuit can be constructed with only OR gates 7 and 11 and flip-flops 7 and 12 as shown in FIG. 7, and the circuit scale can be reduced.

In this way, the CMI encoding circuit according to the present invention inputs the output signal of the CMI code to the determination circuit, compares it with the next input data signal, etc., and sends a clock signal to the final stage output inversion circuit only when necessary. Since we adopted a method of inputting and inverting the output,
When there is no need to invert the level output as a CMI code, the clock signal is not input to the final stage output inversion circuit, so the output inversion circuit does not operate at all, ensuring that glitches do not occur in the output CMI code signal. can be suppressed.

(G) Effects of the Invention According to this invention, a stable CMI code without glitches can be output regardless of the gate delay of each signal in the circuit, so the gate delay amount does not change drastically due to temperature changes. It can be used for transmission equipment located anywhere, and can be used for transmission equipment that has data transmission speeds ranging from low to somewhat high.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is an electric circuit diagram showing an embodiment of the invention, FIG. 3 is a timing chart showing signals of each part in FIG. Figure 4 is a block diagram showing the configuration of the conventional example, Figure 5 is the circuit diagram of the conventional example, and Figure 6 is the circuit diagram of the conventional example.
The figure is a timing chart of the signals of each part in FIG. 5, and FIG. 7 is a diagram corresponding to FIG. 2 showing another embodiment.
FIG. 8 is a timing chart of signals of each part in FIG. 7. 2.1...NRZ code signal input terminal, 2.2...
...Clock signal input terminal, 2, 3, 2, 4, 2,
10～2・13……Flip Flop, 2・5,
2・19, 2・20……EX-OR gate, 2・
6 to 2.9, 2.14 to 2.17...AND gate, 2.18...NAND gate, 2.21...
CMI code signal output terminal.

Claims (1)

[Claims] 1 In a CMI encoding circuit that delays an NRZ code signal and encodes it into a CMI code signal, there is a clock signal generation circuit and an output that inverts the output when receiving a clock signal to form and output a CMI code signal. an inversion circuit, a determination circuit that compares the NRZ code signal and the CMI code signal and outputs a command signal based on the result, and a gate that opens and closes a gate in response to the command signal and supplies a clock signal to the output inversion circuit. and a storage circuit for storing the level of the CMI code signal recently outputted as a storage signal corresponding to 1 of the NRZ code signal, and the determination circuit stores the level of the CMI code signal that is being output when the NRZ code signal is 0. Also, NRZ so that the CMI code signal is 01
It is characterized by outputting a command signal to the gate circuit so that when the code signal is 1, the CMI code signal being output is inverted and becomes 00 or 11 when the NRZ code signal and the storage signal are at the same level. CMI encoding circuit.