JPH0370652U - - Google Patents

Info

Publication number
JPH0370652U
JPH0370652U JP13185989U JP13185989U JPH0370652U JP H0370652 U JPH0370652 U JP H0370652U JP 13185989 U JP13185989 U JP 13185989U JP 13185989 U JP13185989 U JP 13185989U JP H0370652 U JPH0370652 U JP H0370652U
Authority
JP
Japan
Prior art keywords
address
microprocessor
register
area
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13185989U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13185989U priority Critical patent/JPH0370652U/ja
Publication of JPH0370652U publication Critical patent/JPH0370652U/ja
Pending legal-status Critical Current

Links

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  • Microcomputers (AREA)
  • Debugging And Monitoring (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示す構成ブロツク
図、第２図はアドレスデコーダに設けられている
アドレスマツプの構成概念図である。 １…マイクロプロセツサ、２…ＲＡＭ、３…Ｒ
ＯＭ、４…Ｉ／Ｏレジスタ、５…アドレスデコー
ダ、６…プロセツサ停止回路。 FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a conceptual diagram of an address map provided in an address decoder. 1...Microprocessor, 2...RAM, 3...R
OM, 4...I/O register, 5...address decoder, 6...processor stop circuit.

Claims (1)

【実用新案登録請求の範囲】 マイクロプロセツサとこれによりアクセスされ
るメモリ及びＩ／Ｏレジスタを有する装置におい
て、 メモリ領域とＩ／Ｏレジスタ領域のアドレスを
分離して配置すると共に、前記Ｉ／Ｏレジスタ領
域の上部（後のアドレス）に無効領域を設けるよ
うにアドレスを割付けたアドレスマツプを有し、
前記マイクロプロセツサからのアドレスを受けこ
のアドレスマツプに対応してセレクト信号をメモ
リ及びＩ／Ｏレジスタに出力するアドレスレコー
ダと、 このアドレスデコーダが無効領域を検出した信
号を受け、マイクロプロセツサに対して停止信号
を出力するプロセツサ停止回路と を設けたことを特徴とするマイクロプロセツサ装
置。[Claims for Utility Model Registration] In a device having a microprocessor, a memory accessed by the microprocessor, and an I/O register, addresses of a memory area and an I/O register area are arranged separately, and the I/O It has an address map in which addresses are allocated so that an invalid area is provided at the top (later address) of the register area.
an address recorder that receives an address from the microprocessor and outputs a select signal to the memory and I/O register in accordance with this address map; 1. A microprocessor device comprising: a processor stop circuit that outputs a stop signal when the processor stops.
JP13185989U 1989-11-13 1989-11-13 Pending JPH0370652U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13185989U JPH0370652U (en) 1989-11-13 1989-11-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13185989U JPH0370652U (en) 1989-11-13 1989-11-13

Publications (1)

Publication Number Publication Date
JPH0370652U true JPH0370652U (en) 1991-07-16

Family

ID=31679343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13185989U Pending JPH0370652U (en) 1989-11-13 1989-11-13

Country Status (1)

Country Link
JP (1) JPH0370652U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55146553A (en) * 1979-05-02 1980-11-14 Hitachi Ltd Controlling circuit of program of microcomputer
JPS61216059A (en) * 1985-02-21 1986-09-25 Fujitsu Ltd System for protecting storage data
JPS61279940A (en) * 1985-06-05 1986-12-10 Mitsubishi Electric Corp Fault detector for computer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55146553A (en) * 1979-05-02 1980-11-14 Hitachi Ltd Controlling circuit of program of microcomputer
JPS61216059A (en) * 1985-02-21 1986-09-25 Fujitsu Ltd System for protecting storage data
JPS61279940A (en) * 1985-06-05 1986-12-10 Mitsubishi Electric Corp Fault detector for computer

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