JPH0371665A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a high speed MOSFET from deteriorating in service life due to the increase of a drain resistance caused by the accumulation of hot carriers and in breakdown strength due to a short channel effect by a method wherein a gate oxide film under a gate electrode is kept small in thickness. CONSTITUTION:Gate electrodes 6 and 8 are formed, then only in a low speed MOSFET 3 whose gate oxide film is thick, the exposed gate oxide film 5 is removed and a through oxide film 12 is newly formed, and in a high speed MOSFET 4, a gate oxide film 7 is left as it is and a through oxide film 12 is formed thereon at the same time with the low speed MOSFET 3. Therefore, on the high speed MOSFET side, as the thickness of an oxide film under a gate electrode is retained as that of the thin gate oxide film 7 is, hot carriers injected into an oxide film 1 are neutralized with charges injected through the gate electrode 8 and not accumulated. By this setup, a high speed MOSFET can be prevented from deteriorating in service life due to the increase of a low concentration drain offset region in resistance caused by accumulated carriers.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Actions Embodiment 1 Process sectional view of the embodiment (Fig. 1) Invention Effects [Summary] Regarding the improvement of the method of manufacturing semiconductor devices, especially the method of forming multiple MOSFETs with different operating speeds on the same semiconductor substrate, we have improved the method of manufacturing high-speed MOSFETs and low-speed MOSFETs that are less susceptible to performance deterioration due to hot carrier accumulation. For the purpose of forming a semiconductor device in which a semiconductor device is mixedly mounted, a low-concentration diffusion region that becomes a source or drain region with a low impurity concentration and a high-concentration diffusion region that becomes a source or drain region with a high impurity concentration are connected in order from the channel region side. The first slow speed
When forming a MOSFET and a high-speed second MOSFET on the same semiconductor substrate, a first gate insulating film is formed on a first element formation region where the first MOSFET is formed, and the first gate insulating film is A step of forming a second gate electrode on the insulating film, and a second step of forming the second MOSFET.
A second gate insulating film thinner than the first gate insulating film is formed on the element formation region.
forming a second gate insulating film on the second gate insulating film, and selectively forming a first gate insulating film exposed on the first element forming region. a step of forming a third insulating film on the first element formation region and the second element formation region;
The first gate electrode or the second gate electrode is located in the element formation region of
The same impurity is ion-implanted simultaneously through the third insulating film or through the third insulating film and the second gate insulating film using the gate electrode of the first and second MOSFEs as a mask.
and forming the low concentration diffusion region of T at the same time.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for forming a plurality of MOSFETs having different operating speeds on the same semiconductor substrate.

In recent years, MO3ICs have been developed in which analog and digital circuits are installed on the same semiconductor substrate. In this analog/digital mixed MO3IC, analog transistors have a relatively slow operating speed, and analog transistors have a fast operating speed. It is required that digital transistors and digital transistors be mounted together on the same semiconductor substrate.

Therefore, in order to simplify the process and prevent cost increases, we developed a manufacturing method that uses the same process as much as possible to produce both low-speed and high-speed transistors, and that does not degrade the performance or reliability of each transistor. is desired.

[Conventional technology]

In the analog/digital mixed MO3IC,
Low-speed MOSFETs used in analog transistors are constructed of LDD-structured MOSFETs with thick gate insulating films and long channel lengths, while high-speed MOSFETs used in digital transistors are constructed with LDD-structured MOSFETs with thin gate insulating films and short channel lengths. configured.

A first low operating speed MOSFET with a thick gate insulating film and a long channel length, and a second high operating speed MOSFET with a thin gate insulating film and a short channel length.
Conventionally, when forming two on the same semiconductor substrate, the second
The method described with reference to Figures (a) to (a) was used.

Referring to FIG. 2(a), for example, the first MO is defined on one surface of a p-type silicon (Si) substrate by a field oxide film 2 for isolation between elements.
The first element formation region 3 where the SFET is formed and the second
After forming the second device formation region 4 in which the MOSFET is formed, a first device formation region 4 is formed on the first and second device formation regions 3.4.
A first gate oxide film 5 with a thickness of about 500 layers is formed by thermal oxidation, and a first polyester film 5 is formed on the first element formation region 3.
The first gate electrode 6 is formed by forming a first gate electrode 6, etc., and the first element forming region 3 is covered with a resist mask (not shown), and a second gate electrode 6 is formed.
After selectively washing out the first gate oxide film 5 on the element formation region 4, a resist mask (not shown) is applied.
is removed and second thermal oxidation is performed to form the second element forming region 4.
A second gate oxide film 7 having a thickness of approximately 200 layers is formed thereon. Here, an oxide film 7s with a thickness of about 300 layers is formed on the surface of the first gate electrode 6 made of poly-Si,
The first gate oxide film 5 also becomes slightly thicker.

Referring to FIG. 2(b), a second poly-Si layer 10B, for example, which is the material of the second gate electrode, is then formed on the substrate.

Referring to FIG. 2(C), the second poly-Si layer 108 is patterned by active ion etching (RIB) using the first resist pattern 9 as a mask.
A second gate electrode 8 made of a layer is formed. At this time, a second poly 5iN10 layer is applied to the side surface of the first gate electrode 6.
8 residue 8S remains.

Refer to FIG. 2(d) Next, a second resist pattern 10 having an exposed opening 9 is formed on the upper surface of the first element forming region 3, and using this as a mask, a pattern such as (CF, +O□) etc. is formed. The poly-Si layer residue 8s, which causes a short circuit between electrodes and wiring, is removed by isotropic dry etching using gas or the like.

Refer to FIG. 2(e) Next, after removing the second resist pattern 10, the first gate oxide film 5, the second gate oxide film 7, and the first gate are exposed by wet etching using hydrofluoric acid or the like. The oxide film 7s on the surface of the electrode 6 is removed.

At this time, undercut portions 111A, IIIB, and IIA, IIB are formed in the lower portions of the first gate electrode 6 and the second gate electrode 8 near the side surfaces, respectively, by side etching. The width of this undercut portion, that is, the depth of the side etching is approximately 500 Å under the first gate electrode 6 and approximately 1000 Å under the second gate electrode 8.

Refer to FIG. 2(f). Next, thermal oxidation is performed to expose the first element shape t.
On the c region 3 and the second element formation region 4, a thickness of 200 to 3
A through oxide film 12 is formed that transmits impurity ions during ion implantation of approximately 00λ. At this time, a thickening film 12 with a thickness of about 300 to 400 layers is also formed on the surfaces of the first and second gate electrodes 6.8. Due to this oxidation, the lower portions of the gate electrodes 6.8, etc. undercut portion 111A,
The lower ends of the gate electrodes exposed at IIIB, IIA, and IIB are shaved off, and at the lower part near the side of the gate electrode 6.8, there is a cut-in portion 12S of the through oxide film that thickly spreads outward, called a gate bird's beak. , 12t is demonstrated.

Next, using the first and second gate electrodes 6.8 as masks, a film is formed through the through oxide film 12 into the first element formation region 3 and the second element formation region 4 by, for example, l×I Q ” cm.
-” Phosphorus (P゛) at a low concentration of CD, e.g. 40KeV
Ions are implanted shallowly at a low energy level.

113A, 113B, 113G, 113D are low concentration P
4 injection areas are shown.

Figure 2 (see turbidity) Next, silicon dioxide (SiOz) is deposited on the above substrate to a thickness of about 2,000 yen by chemical vapor deposition (CVD).
After shaping the film, the entire surface is etched by RIE processing to form a 2000 mm thick film on the side surfaces of the first and second gate electrodes 6.8.
Forming a side wall 14 of about 02 iO
Ion implantation is performed with high energy of about V.

115^, 115B, 115C, 1150 are high concentration A
s′ injection region is shown.

Refer to FIG. 2(b). Next, a glabellar insulating film 16 made of phosphosilicate glass (PSG) with a thickness of approximately 8000 Å is formed by the CVD method, and source and drain regions are exposed on the interlayer insulating film 16 by ordinary photolithography. Output contact window 17A~
170, and then reflow the interlayer insulating film 16 at a temperature of about 900-1000 DEG C. to form tapers on the side surfaces of the contact windows 17A-170. Due to the temperature of this reflow process, the low concentration P implanted region 113A-
1130 and high concentration As” implanted region 115A-1150
are activated and become n-type low concentration diffusion regions 13A and 13B, which become source or drain regions with low impurity concentration.
, 13C, 130 and n-type high concentration diffusion regions 158, 15B which become source or drain regions with high impurity concentration.
, 15C, 150 are formed.

Referring to FIG. 2(i), the contact windows 174 to 17 are then opened in a conventional manner.
For example, an At wiring 18A having a thickness of about 1 μm on
18D is formed, and thereafter a covering insulating film (not shown) is formed, and an analog/digital hybrid MO3IC having a low-speed MOSFET (Try) with an LDD structure and a high-speed MOSFET (Tr2) with an LDD structure is completed.

[Problem to be solved by the invention]

However, in the analog/digital mixed type MO3IC formed by the above conventional method, first
), the low speed MOS FET (
Tr, ) and high-speed MOS FET (Trz), there are formed through oxide film encroachments 12s and 12t, called gate bird's beaks, directly below the side surfaces of the gate electrodes 6 and 8, which extend outward. Since the thickness of the insulating film is thicker in that part, the lower part of the insulating film and the gate electrode 6
Alternatively, the channel of the n''-type low concentration diffusion region 130 becomes long, especially on the side of the n'' type high concentration diffusion region 150 which becomes the drain to which a high potential is applied to the high speed MOSFET (Trz) having a short channel. Negative charges due to hot carriers (e) generated at the side end faces and injected into the lower layer of the gate bird's beak are no longer neutralized by the potential of the gate electrode 6 and are gradually accumulated in that part, and this negative charge This causes a problem in that the surface layer of the lower n-type low concentration diffusion region 130 becomes depleted and its operating resistance gradually increases, deteriorating the transistor characteristics.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device in which a high-speed MOSFET and a low-speed MOSFET are mounted together, which is less likely to cause performance deterioration due to accumulation of hot carriers.

[Means to solve the problem]

The above-mentioned problem is solved by a low-speed diffusion region in which a low-concentration diffusion region that becomes a source or drain region with a low impurity concentration and a high-concentration diffusion region that becomes a source or drain region with a high impurity concentration are arranged in order from the channel region side. 1 MOSF
When forming an ET and a high-speed second MOSFET on the same semiconductor substrate, a first gate insulating film is formed on a first element formation region where the first MOSFET is formed;
forming an i-th gate electrode on the first gate insulating film; and forming a second gate insulating film thinner than the first gate insulating film on a second element formation region where the second MOSFET is formed. a step of forming a second gate electrode on the second gate insulating film; and a step of selectively removing the first gate insulating film exposed on the first element formation region. and,
forming a third insulating film on the first element formation region and the second element formation region; and forming a third insulating film on the first and second element formation regions; Using the second gate electrode as a mask, the same impurity is ion-implanted simultaneously through the third insulating film or through the third insulating film and the second gate insulating film to form the first and second MOSFETs. This problem is solved by the method of manufacturing a semiconductor device according to the present invention, which includes a step of simultaneously forming the low concentration diffusion region.

[For production]

That is, in the present invention, after the gate electrode is formed, the gate oxide film that exposes only the low-speed MOSFET with a thick gate oxide film is removed and a new through oxide film is formed to form a high-speed MOS
For the FET, the gate oxide film is left as is, and a through oxide film is formed on top of it at the same time as the low-speed MOSFET.

As a result, on the high-speed MOSFET side, when forming a through oxide film, the through oxide film does not dig into the lower part of the gate electrode, which is called a gate bird's beak, and the oxide film thickness under the gate remains the same as the thin gate oxide film. As a result, the hot carriers injected into the oxide film are neutralized by the charges injected from the nearby gate electrode and are no longer accumulated, and the low-concentration drain caused by the accumulated carriers is This prevents the life of the high-speed MOSFET from decreasing due to high resistance in the 6Jf offset region.

At the same time, when implanting impurity ions to form source/drain regions, the total oxide film thickness through which ions pass is thicker for high-speed MOSFETs.
The depth of ion implantation in simultaneous ion implantation using the same energy is shallower in the high speed MOSFET, which also has the effect of preventing short channel formation in the high speed MOSFET.

(Example) An example of the method of the present invention will be described below with reference to FIGS.
This will be explained in detail with reference to (e).

Refer to FIG. 1(a) By the method of the present invention, a low concentration diffusion region which contacts the channel region side and becomes a source or drain region with a low impurity concentration, and a high concentration diffusion region which becomes a source or drain region with a high impurity concentration. When forming an analog/digital hybrid MO3IC in which a low-speed MOSFET and a high-speed MOSFET of an LDD structure are formed on the same semiconductor substrate, first refer to FIGS. 2(a) to (d). A low operating speed first MOS FET on a p-type Si substrate l is fabricated by a process similar to the conventional method described above.
A first gate electrode 6 made of, for example, poly-Si is formed on the first element formation region 3 formed by (Try), with a first gate oxide film 5 having a thickness of, for example, about 500 Å interposed therebetween.
High operating speed second MOS FET (Trz)
A substrate to be processed is formed on which a second gate electrode 8 made of, for example, poly-Si is formed, with a thin second gate oxide film 7 of about 200 layers being formed on the second element formation region 4 formed with Form. Note that 7s is an oxide film with a thickness of about 300A formed at the same time as the second gate oxide film 7, and 10 is an oxide film formed on the side surface of the first gate electrode 5 when forming the second gate electrode 8, as explained in the conventional method. This is a resist pattern used as an etching mask when removing the residue 8s (not shown) of the polySt layer which is the material of the shaped second gate electrode 8.

Refer to FIG. 1(C), and in the method of the present invention, the resist pattern 1O or a newly formed resist pattern (not shown) having openings extending wider and exposing the first element forming region 3 is used. is used as a mask, and with this resist pattern covering the second element forming area 4, the first element forming area 3 is
Only the first gate oxide film 5 exposed above is selectively removed by wet treatment using hydrofluoric acid or the like.

Here, the oxide film 7s on the surface of the first gate electrode 6 is removed, and undercut portions 111A and IIIB similar to the conventional one are formed under the first gate electrode 6.

Refer to FIG. 1(C) Next, after removing the resist pattern 1O, a thickening film 12 having a thickness of about 200 to 300 layers is formed on the 3 surfaces of the first element formation region exposed by, for example, thermal oxidation. do.

At this time, a gate bird's beak 12s is formed under the first gate electrode 6 as in the conventional case, but the end surface of the second gate oxide film 7 exposed on the second element formation region 4 is exposed. Because they have not done so, there is a large number of people in total, about 100 to 200 people.

Therefore, no gate bird's beak is formed under the second gate electrode 8.

Referring to FIG. 1(d), a conventional method is used to pass through the through oxide film 12 or the gate oxide film 7 using the gate electrodes 6 and 8 as masks using a method similar to that described with reference to FIG. 2(f). 1,
A low concentration of Po is ion-implanted into the second element formation region 3.4, and then SiO □ The through oxide film 1 is formed by forming the sidewall 14 and using the gate electrode 6.8 having the sidewall 14 as a mask.
2 or the first and second element formation regions 3.115A, 115B, 115C11150 through the gate oxide film 7.
indicates a high concentration As' implanted region.

Referring to FIG. 1(e), a glabellar insulating film 16 is then formed on the substrate as in the conventional method.
After shaping the contact windows 17A to 170 in the source/drain regions, a glue flow process is performed on the glabella insulating film 16 to form a taper on the side surface of the contact windows 17A to 170, and at the same time, the P' and As' implanted regions are activated to reduce the n-type low concentration diffusion region 1 which becomes a high concentration source or drain region
3A, 13B, 13C, 130 and an n-type high concentration diffusion region 15 which becomes a high concentration source or drain region.
A, 15B, 15C, 150 and then Al
After the wirings 18A to 18D are formed, a covering insulating film (not shown) is formed, and low-speed MO
S F E T (Tr+) and high speed MOS F E T
(Trz)
3IC is completed.

As is clear from the above description of the embodiments, according to the method of the present invention, high-speed MOS F E
Under the gate electrode 8 of T, the gate oxide film 7 exists with its thin thickness maintained as it is without producing a part called a gate bird's beak where the thick oxide film digs. Therefore, the hot carriers injected into the gate oxide film 7 are neutralized by the charges injected from the gate electrode 8 and are no longer accumulated in the gate oxide film 7, so that the hot carriers become a low concentration drain region formed under the gate oxide film 7. High resistance of the low concentration diffusion region 15D is prevented.

In addition, the thickness of the oxide film through which ions pass when forming source/drain regions is thicker on the high-speed MOSFET side, so the source/drain regions can be formed shallower in high-speed MOSFETs, preventing short channel effects. be advantageous to

Note that in the method of the present invention, the gate oxide film and the through oxide film may be insulating films formed by vapor phase growth.

[Effect of the invention] As explained above, according to the method of the present invention, low-speed MOSF
In analog-digital hybrid MO3ICs in which an ET and a high-speed MOSFET are formed on the same semiconductor substrate, life deterioration due to an increase in drain resistance due to the accumulation of hot carriers in a high-speed MOSFET with a short channel, and breakdown voltage deterioration due to the short channel effect. etc. are prevented.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are process sectional views of an embodiment of the method of the present invention, and FIGS. 2(a) to (i) are process sectional views of a conventional method. 17A to 170 are contact windows, 18A to 180 are old wirings, 113A to 113D are low concentration P injection regions, 115A
˜1150 indicates a high concentration As' implantation region. In the figure, l is a p-type Si substrate, 2 is a field oxide film, 3.4 is the first and second element formation region, 5.7 is the first and second gate oxide film, 6.8 is the first , second gate electrode, 9.10 is a resist pattern, 11A, IIB, IIIA, IIIB are undercut parts, 12 is a through oxide film, 12s is a gate bird's beak, 13A to 130 are n-type low concentration diffusion regions , 14 is SiO
□Side wall, 15A to 150 are n-type high-concentration diffusion regions, 16 is an insulating film between the eyebrows, Figure %2 (No. 1) Figure 2 (No. 2)

Claims (1)

[Scope of Claims] A low-concentration diffusion region comprising a low-concentration diffusion region that becomes a source or drain region with a low impurity concentration and a high-concentration diffusion region that becomes a source or drain region with a high impurity concentration that are in contact with each other in order from the channel region side. When forming a first MOSFET and a high-speed second MOSFET on the same semiconductor substrate, a first gate insulating film is formed on a first element formation region where the first MOSFET is formed; forming a first gate electrode on a first gate insulating film; and forming a second gate insulating film thinner than the first gate insulating film on a second element formation region where the second MOSFET is formed. a step of forming a second gate electrode on the second gate insulating film; a step of selectively removing the first gate insulating film exposed on the first element formation region; forming a third insulating film on the first element formation region and the second element formation region; and forming a third insulating film on the first and second element formation regions; Using the second gate electrode as a mask, the same impurity is ion-implanted simultaneously through the third insulating film or through the third insulating film and the second gate insulating film to form the first and second MOSFETs. A method for manufacturing a semiconductor device, comprising the step of simultaneously forming the low concentration diffusion region.