JPH0371717A - Logic circuit - Google Patents

Abstract

PURPOSE:To realize a stable ultrahigh speed circuit by providing a clamp circuit clamping a level of an output node of a logical section in parallel with a FET or a component deciding a power supply, and using the clamp circuit so as to make a level difference between the output node of the logical section and the power supply constant against a change in the power voltage. CONSTITUTION:A clamp circuit 107 is provided in parallel between a gate electrode of a FET and an N pole of a Schottky diode formed with a gate electrode and a source electrode of FETs 201, 204 of a next stage circuit 200, that is, a negative power supply. Thus, the circuit acts like making the level difference between the electrodes constant against the power voltage fluctuation. Thus, the current change in the next stage is much reduced. Moreover, the clamp circuit 107 consists of the FETs 201, 204 and a Schottky diode, so long as the current flowing to the clamp circuit 107 depends on other component, the current flowing to the next stage is unchanged against the dispersion in the Vth of the FET. Thus, a current Iout is made stable.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic circuits, and particularly to GaAs logic circuits that are extremely high-speed and operate stably.

[Conventional technology]

The prior art is discussed, for example, in IEE Transactions on Electron Devices, Eday 25, No. 6 (1970), pages 628 to 639.

FIG. 18 shows a conventional high-speed circuit shown in the above-mentioned document. This circuit is used particularly in fields where high speed is required, and has a positive side power supply (for example, 0V) 151,152 and a negative side power supply (for example, -2V) 153, and a field effect transistor (hereinafter referred to as FET) 101. ,102,104,10
5.106, and a load element 103 consisting of an FET or the like. Input terminal 155 is connected to the gate electrode of FET 10I, 104. Similarly, other input terminals are FET1
Connected to 02.105. The output terminal 157 is an FET
It is drawn out from the connection point between the source at 106 and the common drain electrode at 104° and 105.

The operation of this logic circuit is such that either input terminal 155 or 156 receives a logic high level (e.g., -1,
4V) is applied, output terminal 157 has a logic low (L
OW) level (e.g.

-2, OV) appears.

The logic operation is mainly performed by FETl0I, 102 and load element 10.
3, for example, when the input terminal 155 is high
When the voltage is at the level, a current flows through the FETl0I, and this current flows through the load element 103, so that the potential of the connection 120 decreases and becomes close to the negative power supply voltage. Therefore, a logic low level (virtually a negative power supply voltage) also appears at the source of FETl0I, that is, at the output terminal 157. On the other hand, when a logic low level is applied to all input terminals, no current flows through the load element 103, so the connection 1
The potential of 20 becomes almost the positive power supply voltage, and the output terminal 157
A logic high level appears. The voltage value depends on the type of gate circuit in the next stage, but when the exact same circuit as shown in Fig. 18 is connected, it is a logic high (High).
The level is higher than the negative power supply voltage by Vf. Here, Vf is, for example, when the input terminal 155 is high (High
) level, this is the forward voltage of the Schottky junction formed between the gates and sources of FETs 10I and 104. If Vf is about 0.6■, when the negative power supply voltage is 12V, the high level is about -1
, becomes 4V.

FETs 104 and 105 are used to shorten the delay time, and in particular, quickly discharge the load capacitance when the input signal rises, thereby speeding up the fall of the output signal. On the other hand, when the input falls, the FET 106 charges the load capacitance at a high speed to speed up the rise of the output signal.

[Problem that the invention seeks to solve]

The problem with the conventional technique shown in FIG. 18 is that the circuit current varies greatly.

Assume that the circuits shown in FIG. 18 are connected in cascade. The circuit at an arbitrary stage will be called the first stage, and the circuit at the next stage will be called the next stage. Also, for simplicity, consider a case where FETs 102 and 105 are not present. It is assumed that the output terminal 157 of the first stage is connected to the input terminal 155 of the next stage. When this connection point is at a logic low (Low) level, current flows from the first stage FET 106 to the first stage FET 104. This value is
It is determined by the difference between the potential of 20 and the potential of output terminal 157. No current flows to the next stage. On the other hand, when this connection point is at a logic high level (High), the first stage FET 104 is cut off and no current flows, and the current path is connected to the first stage FET 104.
From 06 onwards, it becomes a Schottky diode between the gate and source of FET 10I and 104 in the next stage. The potential of the output terminal 157 is determined so that the current flowing through the Schottky diode and the FET 106 are equal, and the current value is determined.

However, Schottky diodes and FETs
Each has current-voltage characteristics of an exponential function or a square function, and the current is determined by reacting extremely sensitively to voltage. Therefore, if the potential difference between the connection 120 and the negative power supply 153 changes even slightly, the current changes greatly. In this case, since the connection 120 is approximately equal to the potential of the positive power supply, this ultimately means that the current in this circuit varies greatly depending on the power supply voltage.

Further, even if the power supply voltage does not change, the above-mentioned current flowing to the next stage changes greatly depending on the threshold voltage Vth of the FET 106.

That is, in the conventional technology, since the circuit current largely depends on the power supply voltage and the vth of the FET, there is a problem in that variations in characteristics, particularly delay time, etc., become extremely large.

The object of the invention is, as mentioned above, to reduce the circuit current.

Eliminates large dependence on power supply voltage and FET vth,
The object of the present invention is to provide a logic circuit with small variations and stable operation.

Means for Solving Problem c] The logic circuit of the present invention is provided with a clamping circuit for clamping the potential of the logic output node in parallel with the FET or element that determines the current, and by this clamping circuit, the power source is It is characterized by keeping the potential difference between the logic output node and the power supply constant despite changes in voltage.

In addition, by using an element similar to the FET or element that determines the above-mentioned current in the clamp circuit, it is possible to increase the vth of the FET.
Extremely stable characteristics are achieved even with variations.

[Effect]

The above clamping circuit is connected to the FET's goo 1-electrode.

Since it is provided in parallel between the N pole of the Schottky diode, that is, the negative power supply, it functions to keep the potential difference between the electrodes constant even when the power supply voltage fluctuates. Therefore, changes in the current flowing to the next stage can be made extremely small. Furthermore, by configuring the clamp circuit with a FET and a Schottky diode, as long as the current flowing through the clamp circuit is determined by other elements, the current flowing to the next stage will vary depending on the Vth variation of the FET. There's nothing to do.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the invention. This circuit is.

It operates under positive power supplies 151 and 152 and negative power supplies 153 and 154, and output signals are obtained at output terminal 157 in response to input signals applied to input terminals 155 and 156. The logic function is the same as the conventional example shown in FIG. Pull-up movement FE to increase opening ability
It is T. Further, 103 is a load element, and the input terminal 1
As a result of changing the voltage drop across 55.156 in response to the input signal applied to it, a logic high (High) is applied to connection (logical output node) 120 and further to output terminal 157.
Alternatively, a low level output signal appears. Element 107 is a clamp element and plays a central role in this embodiment.

For a detailed explanation of this embodiment, reference is made to FIG. Here, for the sake of simplicity, the positive power supplies 151- and 152 and the negative power supplies 153 and 154 are common, respectively, and only one input terminal is provided. Further, this figure shows only one circuit in a certain arbitrary stage and a part of a similar circuit connected to its output terminal. In other words, F E T 20↓, 204 in the next stage circuit 200 is the first stage circuit 100.
This corresponds to 101.104.

When a high level input signal is applied to input terminal 155 of circuit 100, FETl0I.

1.04 becomes conductive, and the load element 103 is connected to the FET
Current flows to l01. As a result, the connection 120 has a potential close to the negative power supply voltage. Depending on the potential, a relatively small amount of current flows from FET 106 to FET 104. No current flows through the circuit 200 at the next stage.

On the other hand, when the input signal of the circuit] and OO is at the (Low) level, the FETl0I, 1.04 becomes non-conductive, so the current from the load element 103 does not flow to the FETl0I, and the clamp element] Flows to -07. As a result, due to the voltage drop across the clamp element, the connection 120 becomes at a potential higher than the negative power supply voltage by the voltage drop. Also, FET1
Since the voltage between the source and gate of 06 becomes large, the FET
A relatively large current tries to flow through 106, but FE
Since T104 is in a non-conducting state like FETl0I, the current from FET106 is transferred to the FET of the next stage circuit 200.
The current flows through a Schottky diode formed by the gate and source electrodes of 201 and 204. The present invention relates to this electrical work. The purpose is to stabilize ut. In this state, the following relational expression holds true.

V (120) = V g s (FET106)+
V f (FET201, 204) = Vf (element 10
7) -～-(1) Here, V (120) is the potential difference between the connection g120 and the negative side power supply voltage, V g s (
FET106) is FET], 06 game l~・
The source voltage, V f (FET201, 204) is F
E T 20 ], , the forward voltage drop of the parallel Schottky diode of 204, Vf (element 107) is the forward voltage drop of element 107. Iout is V g
The square function characteristic of s (FET106), V f (F
It is determined by the exponential characteristic of ET201°204). Therefore, even a slight change in V(120) can cause a large change in rout; however, in the present invention, when V(120) is
7). Therefore, element 10
If the current flowing through 7 does not depend much on the power supply voltage etc., Vf (element 107), v (120), and Iout
The change in can be made extremely small.

In addition, the element 107
Furthermore, by using the same type of elements as the Schottky diodes of FET 106 and FETs 201 and 204, the influence of these fluctuations can be minimized. For example, F.E.
When the vth of T106 becomes low, the same V(120)
However, if the current of element 107 is also subject to the same fluctuation of Vth, the voltage drop will become smaller for a certain current, and V(120) will become lower. This acts to reduce Iout to its original value.

For a more detailed explanation of the above-mentioned operation, reference is made to FIG. Figure 3 shows the clamp circuit 10 in Figures 1 and 2.
7 shows some specific configuration examples. In FIG. 3(a), the clamp circuit is constructed by connecting an FET 301 and a Schottky diode 302 in series.

FET301 has the same Vth design as FET106.
ET, and the Schottky diode 302 is an FET 20 that receives the output of the first stage circuit in the first stage circuit 200.
It has the same Vf design as a 1.204 gate-source Schottky diode. Practically speaking, it is considered that the vth or Vf of devices simultaneously formed on the same semiconductor substrate with the same implantation amount of impurities of the same energy are almost the same. For simplicity, the dimensions are also FE
Assuming that T301 is the same as FET106 and Schottky diode 302 is the same as the Schottky diode between the gate and source of FET201.204 (7), the current Ic flowing through the clamp circuit 107 and the current I
out will be almost the same.

This is because the voltage applied across the clamp circuit 107 is exactly the same as the voltage applied to the series circuit of the FET 106 and the Schottky diode between the gate and source of the FETs 201 and 204. By the way, the current value is determined only by the current of the load element 103 because all the current of the clamp circuit 107 is supplied from the load element 103. Therefore, by making the characteristics of the load element desired, it is possible to obtain a desired stable Iout. Incidentally, if the dimensions of the elements of the clamp circuit are made n times larger than the Schottky diode between the gate and source of FET 106 or FETs 201 and 204, Ic in the clamp circuit flows n times as much as Iout.

FIG. 3(b) is an example of another implementation means of the clamp circuit 107. Here, the Schottky diode 302 in FIG. 3(a) is replaced with an FET 303. FE
The gate electrode of FET 303 is connected to the source electrode of T301, and a Schottky diode is used between it and the source and drain electrodes. In addition, Fig. 3 (c
), it is also possible to use only a Schottky diode between the gate electrode and the source or drain electrode of FET 304.

FIG. 3(d) is an example of still another means for realizing the clamp circuit 107. Here, FET 30 in FIG. 3(b)
3 is replaced with two FETs 305 and 306. By doing this, the voltage drop Vf (element 107) of the clamp circuit at a certain current Ic can be reduced by
It can be easily changed depending on the number of connections of 05 or 306. Similarly, the same effect can be expected by connecting the same type of FET in parallel to the FET 301 or by increasing the gate width of the FET 301. Therefore, the output current Io
ut can be changed. This method is effective when the number of circuits connected to the output terminal of one circuit, that is, the number of fan-outs increases. FIG. 4 shows an example where the fanout is 2.

In this figure, four circuits 400 to 403 are connected to each other, circuit 400 has a fanout of 1, and circuit 401 has a fanout of 2. In this way, when the fan-out increases, the same V f (FET201, 2
04) On the other hand, since the current of the Schottky diode becomes large, Iout also becomes large. At times like this,
With the structure shown in Figure 3(d), FETs such as 305, 306 etc.
By increasing the number of connections, the Vf of the clamp circuit (element 1
07) and reduce Iout.

Furthermore, if the load wiring length is long, it may be necessary to increase Iout to reduce the delay time. In this case, by reducing the number of connected FETs such as 305 and 306, Vf (element 107) of the clamp circuit can be increased, contrary to the above, and Iout can be increased. of course,
This is also possible by changing the gate width of FETs 305 and 306.

However, except in special cases, FET30
When the gate width of 1 is made n times that of FET 106,
The total gate width of 305 and 306 is also 201 and 201 in Figure 2.
It is preferable to make the width n times the total gate width of 204 gates (if a large number of fan acs l- are used, the total of all of them). Note that, as is clear from the above explanation, for example, FIG. 3(a)
, FET30] and Schmittkey diode 30
The connection order of 2 may be reversed. That is, the anode of the diode 302 may be connected to the connection 120, the drain D1- of the FET 301 may be connected to the cathode of the connection 120, and finally the source of the FET 301 may be connected to the negative power supply 153. This also applies to FIGS. 3(b) to 3(d).

FIG. 5 shows another embodiment of the invention. here.

An example of a method for concretely realizing the load element 1.03 of FIG. 1 is shown. FET503 is a normally-on type FET.
ET, whose gate and source electrodes are connected to each other. As a result, when the potential difference between the connection (logic section output node) 120 and the positive power supply 151 is sufficiently large, the FET5
The current flowing through 03 becomes almost a constant current.

FIG. 6 shows still another embodiment of the present invention. here,
The load element 103 in FIG. 1 is a normally-on type FET 60.
3, and a fixed potential Vg is applied to the group 1 as a bias.

FIG. 7 shows an example of a circuit for generating the above-mentioned Vg. Here, FET703.712,101 is a normally-off type, and FET709.711゜713.714,60
3 is a normally-on type FET. Also, 702.7
05 is a diode. This circuit uses a circuit similar to that shown in FIG. 6 as the circuit 600, and connects the potential Vg to the wire 753.
It is connected to the gate of the FET 603 in the circuit 600, and at the same time, the source potential of the FET is fed back through the connection 752. Kyu 1IX7
The potential of 52 is automatically adjusted to approach the potential of connection 750.

Let's explain its operation. The gate electrode of FET709 has
Connection 750 provides some desired bias. This bias is generated by a circuit consisting of resistors 704, 706, 707 and diode 705. In other words, there is a certain voltage across the diode 705, for example 0.
A voltage of 5V is generated, and this value hardly changes even if the power supply voltage changes slightly, as long as the potential difference between both ends of the resistor 704 is large enough. Therefore, when dividing resistors 706 and 707 are connected in parallel with this diode 705, a value obtained by dividing the voltage of the diode 705 is generated at the connection point 750 between the resistors 706 and 707, which is almost unaffected by changes in the power supply voltage. . Moreover, since no FET is used, it is not affected by the threshold voltage vth of the FET. So, for example, resistor 7
If the resistance ratio between 06 and 707 is 223, the potential difference between the connection 750 and the negative power supply 153 will be 0.3V. This connection 7
The potential of 50 and the potential of connection 752 fed back from circuit 600 are compared by a differential transistor circuit. Now, if the Vth of FET603 becomes lower than the design value and the current increases, in this case, FET603
The source potential of increases. Therefore, the potential of connection 752 is higher than the potential of connection 750. Then, FET70
More current flows to FET 711 than 9, and connection 75
The potential of 4 decreases. Therefore, in response, the potential Vg of 753 also decreases, and the potential of connection 752 is automatically adjusted to approach the potential of connection 750. In other words, by lowering Vg, the current returns to the desired design value.

Note that the circuit composed of the resistor 701, the diode 702, and the FET 703 is for supplying a bias potential to the gate of the FET 712 through the connection 751. When the potential difference across the resistor 701 is sufficiently large, the potential difference between the connection 751 and the negative power supply 153 is not affected by the power supply voltage.

Therefore, the current in FET 712 is stabilized, and the potential difference across resistor 710 and the potential at connection 754 are less susceptible to the power supply voltage. Further, a source follower composed of FETs 713 and 714 serves as a buffer for connecting connection 753 to many circuits 600. When the gate widths of FETs 713 and 714 are equal, the gate and source electrodes of FET 714 are shorted, so connection 754
The potentials of and 753 are almost equal.

According to this circuit, the dependence of the current flowing through the FET 603 on vth can be made extremely small.

Therefore, it is possible to stabilize circuit characteristics such as delay time.

FIG. 8 shows still another embodiment of the present invention. This is a case where the present invention is applied to the logic circuit proposed in Japanese Patent Application No. 1-13903. In Fig. 8, compared to Fig. 6, FET
801 is added.

Similar to this FET+JFET 106, it serves to speed up the rise of the output signal.

FIG. 9 shows still another embodiment of the present invention. In this embodiment, the configuration of the clamp circuit 107 is different from the embodiment shown in FIG. The load element 603 is.

An FET 503 as shown in FIG. 5 may be used. In this embodiment, the signal amplitude of the output terminal 157 is transferred to the FET of the next-stage circuit that receives this signal (if the next-stage circuit has the same circuit configuration as the first-stage circuit, it corresponds to 101.104 or 102.105). This is effective when increasing the speed by making the Vf (forward voltage drop) smaller than the Vf (forward voltage drop) of the Schottky diode between the gate and source. For this purpose, a FET 902 is provided between the output terminal 157 and the negative power supply 153. As a result, when the output terminal 157 is at a logic high level, most of the current flows from the FET 106 to the FET 902 instead of from the FET 106 to the Schottky diode in the next stage circuit. As a result, corresponding to equation (1), the potential difference V(120) between the connection 120 and the negative power supply is V(120)=V g s (FE
T106) + V g s (FET902) = V g
s (FET301) + V g s (FET901)---(2). Here, V g 8 (FETXXX) is FET
The gate-source voltage V g s of xxx. No. (
2) In order to hold the formula, the clamp circuit 107 must be F
It is composed of an ET301 and a FET901, and the gate electrode of the FET901 is connected to the output terminal 157 like the FET902. By doing this, as in the explanation up to FIG. 8, all the current flowing in the clamp circuit is supplied from the load element 603, so the output current I You can get something.

FIG. 10 is a modification of the embodiment shown in FIG.
ET901.902 respectively resistor 1001.1002
is replaced with

FIG. 11 shows still another embodiment of the present invention.

Here, a circuit 1100 runs through a circuit 1101 and a circuit 102. However, the input of the circuit 1101 is
The input of the 1 circuit 1102 is connected to the output terminal 1104 of the FET 1103. This configuration is effective when the circuit 1102 is located very close to the circuit 1100 and the negative circuit 1101 is located relatively far away. Further, it is extremely effective when it is desired that the signal propagation to the circuit 1102 does not depend on the magnitude of the load on the output terminal 1104, for example, the wiring length to the circuit 1101 in this example.

In this example, the clamp element in circuit 1100 is an FE
T1103 and FETs 1111 and 11 in circuit 1102
It consists of a series circuit with 14 gate-source Schottky diodes. In other words, the FET in Figure 6
The input FET of the next stage circuit is used instead of 303. Even if the load on the output terminal 1104 becomes heavy, it hardly affects the response of the connection 120, so that a signal can be sent to the circuit 1102 with a constant delay time.

The application of this embodiment will be explained in some detail.

FIG. 12 shows the configuration of a so-called RS flip-flop. In (a), NOR gates 1205 and 1206 constitute an information holding section.

NOR gates 1207 and 1208 serve as buffers for load fluctuations. This is also to prevent the feedback speed of N0R 1205 and 1206 from depending on the load of this flip-flop. However,
With this configuration, not only the number of NOR gates is large, but also
From input terminals 1201 and 1202 to output terminals 1203 and 1
There is a drawback that the delay time up to 204 becomes long.

Therefore, by applying the circuit shown in Fig. 1, Fig. 12 (b)
configuration is possible. Here, NOR gate 1215.
1216 has the configuration of the circuit 1102 in FIG. I1, for example, the output terminal 1204 of N0R1, 215
and 1211 correspond to the output terminal 1104 and the source electrode of the FET 1103, respectively, in accordance with FIG. Therefore, when FIG. 12(b) is expressed in more detail, it becomes as shown in FIG. 13.

FIG. 14 shows still another embodiment. here.

In order to realize the same function as the embodiment shown in FIG. 11, a normally-on type FET 1401 is inserted between the source electrode of the FET 1103 and the negative power supply 153.

This FET 1401 has constant current characteristics because the gate electrode and source electrode are shorted.

If this current value is set to a relatively small value, when the input is at a logic low level, the current flowing from FET 603 will be:
Most are FET1103 to FET]-↓11 and 1
It flows to 114. In other words, the clamping operation of connection 120 connects FET 1103 and FETI 111 and 1114.
Since it is determined by a circuit consisting of

Further, when the input signal rises, the potential of the connection 1105 is discharged by the FET 1401 and falls rapidly. FET 1401 may be a resistor with a relatively large value.

FIG. 15 is a modification of the embodiment shown in FIG. 14. In this embodiment, FET1401 in FIG.
501 and 1502 have been replaced. FET1501
The gate electrodes of and 1502 are connected to the input terminal In1O, respectively.
and In1l. This is to speed up the fall of the second output terminal 1105, and
When l0 or In1l rises, output terminal 110
5 rapidly.

FIG. 16 shows yet another embodiment. In this example, the FET
The source electrodes of FET 301 and FET 106 are connected to each other. In this circuit, the clamp circuit is composed of FET 301 and FETIO1-105 of the next stage circuit, as in the embodiments shown in FIG. 11 and thereafter. 4f like this
If you leave it alone.

Compared to Fig. 15, the number of output terminals is one.

Pull-down FET1501.1502.104.10
5 can be shared only by 104 and 105. Further, the current flowing through the clamp circuit can be effectively used for charging and discharging the output terminal 157.

FIG. 17 shows still another embodiment. This is an application of the concept of the embodiment shown in FIG. 14 to FIG. 6th
A normally-on type FET 1701 is inserted between the source electrode of the FET 106 and the negative power supply 154 instead of the pull-down FETs 104 and 105 shown in the figure. This configuration allows the number of FETs to be reduced. The output fall of the output terminal 157 is accelerated by the discharging operation of the FET 1701.

In addition, from Figure 3 onwards, a gate/clamp circuit is included in a part of the clamp circuit.
The FET 301 with its drain shorted is used in order to correspond to the output pull-up FET 106 and to satisfy equations (1) and (2). However, when it is not necessary to satisfy such an accurate condition, a diode such as a Schottky diode may be used. Also, the 9th
Although the FET 603 is used as the load element 103 in the figures and subsequent figures, it is clear from the above description that the FET 503 as shown in FIG. 5 may be used, or a simple resistor may be used.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to realize an ultra-high-speed circuit that is extremely stable against fluctuations in the electric voltage and the vth of the device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention, and FIGS.
FIG. 7 is a diagram showing an embodiment of the present invention, and FIG. 18 is a diagram showing a conventional example. [Explanation of symbols] 101, 102, 104, 105゜10
6...FET, 103,503,603...Load element, 107...Clamp circuit, 301,303゜9
01.1001, 1103.1301-1 Element for configuring lamp circuit, 902, 1002° 1401.1
701...Pull-down element. (a) (b) (d) (C) 01 03 In+-TnS Input duck) ○U↑1~O, A2 Output salt l 0 94 1s3 1st (d) 1216 Hee LS3 1':A

Claims (1)

[Claims] 1. Provided between a first terminal connected to a first power source and a second terminal connected to a second power source, the first load element and at least one field effect The first transistor
a transistor group, and receives an input signal at the gate of the field effect transistor constituting the first transistor group and outputs a desired logic signal corresponding to the input signal to the first transistor group.
a logic section obtained from a connection point between the load element and the first transistor group; a drain is connected to a third terminal connected to a third power supply; a gate receives the output of the logic section; a first field effect transistor that obtains an output signal from the transistor; and a fourth terminal connected to the source of the first field effect transistor and a fourth power supply, and when the output signal falls, the load is applied. A logic circuit comprising: a pull-down means for discharging a capacitor; and a clamp means provided between the second terminal and the gate of the first field effect transistor. 2. The clamping means comprises a second field effect transistor and a first Schottky diode connected in series between the second terminal and the gate of the first field effect transistor. 2. The logic circuit according to claim 1, wherein: 3. The logic circuit according to claim 2, wherein the threshold value of the second field effect transistor is substantially equal to the threshold value of the first field effect transistor. 4. The pull-down means comprises at least one field effect transistor whose gate is applied with a respective input signal corresponding to each input of the first transistor group, and whose sources are connected to each other to 4. The second field effect transistor comprises a second group of transistors connected to the terminal of the field effect transistor No. 4, the drains of which are connected to each other and connected to the source of the first field effect transistor. The logic circuit described. 5. The first Schottky diode is constituted by a Schottky diode between the gate and source of a field effect transistor having a threshold substantially equal to a threshold of a transistor in the next stage that receives the output signal. 5. The logic circuit according to claim 2, characterized in that: 6. The logic circuit according to claim 1, wherein the first load element is composed of a normally-on field effect transistor. 7. The logic circuit according to claim 6, wherein the normally-on field effect transistor constituting the first load element has a gate and a source connected to each other. 8. The logic circuit according to claim 6, wherein a normally-on field effect transistor constituting the first load element has a gate supplied with a predetermined voltage. 9. Consisting of at least one field effect transistor in which an input signal is applied to the gate of each transistor, the sources of each transistor are connected to each other and connected to a negative power supply, and the drains of each transistor are connected to each other. a first transistor group; a first load element connected between a common drain of the first transistor group and a positive power supply; and a connection between the common drain of the first transistor group and the first load element. a first field effect transistor whose gate is connected to a point; and at least one field effect transistor whose gate is applied with a respective input signal corresponding to each input of the first transistor group; a second group of transistors whose sources are connected to each other and connected to the negative power source, and whose drains are connected to each other and connected to the source of the first field effect transistor; the negative power source and the first field effect transistor; and a clamping means provided between the first field effect transistor and the gate of the first field effect transistor.
A logic circuit characterized in that an output signal is obtained from a source of a field effect transistor. 10. The clamping means is characterized by comprising a second field effect transistor and a first Schottky diode connected in series between the negative power supply and the gate of the first field effect transistor. 10. The logic circuit according to claim 9. 11. The threshold value of the second field effect transistor is
11. The logic circuit of claim 10, wherein the threshold is substantially equal to the threshold of the first field effect transistor. 12. The first Schottky diode is constituted by a Schottky diode between the gate and source of a field effect transistor having a threshold substantially equal to a threshold of a next-stage transistor that receives the output signal. The logic circuit according to claim 10 or 11, characterized in that: