JPH0371789B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device suitable for a master slice type gate array LSI suitable for LSI production of a wide variety of products in small quantities.

What is a master slice type gate array LSI?
Of the ten or so photomasks used when manufacturing LSIs, only the masks corresponding to the wiring are created according to the product being developed to manufacture LSIs with the desired electrical circuit operation. It is said that the concept of master slicing has been around since the 1960s.

Figure 1 shows the configuration of a conventional gate array LSI. The semiconductor chip 10 has a bonding pad and an input/output circuit area 14 on its outer periphery, and has a basic cell 11 consisting of elements such as transistors inside.
The basic cell rows 12 arranged in the axial direction are connected to the wiring area 13.
The structure is such that a large number of them are arranged side by side in the y-axis direction with the two sides in between. In order to obtain the desired electrical circuit operation, one or several adjacent basic cells 11 are connected.
Forms NAND gates, flip-flops, etc.
One LSI is constructed by wiring various logic gates formed by a plurality of basic cells 11 according to a logic diagram.

FIG. 2 shows a plan view of an example of the basic cell 11.
The basic cell 11 includes a P ⁺ type region 2 which becomes the source or drain of a P channel type MOS transistor.
0, an N ⁺ type region 21 that becomes the source or drain of an N channel type MOS transistor, and a P region formed in the N type substrate to form the N ⁺ type region 21.
- WELL region 25, poly-Si gate electrodes 22 of P- and N-channel MOS transistors, Vcc power line 26 that supplies power to both transistors, GND power line 27, P ⁺ that becomes the source or drain,
Consists of a contact hole 24 for connecting the N ⁺ diffusion layers 20, 21 and an Al wiring (not shown), and a contact hole 23 for connecting the poly-Si forming the gate electrode 22 and the Al wiring. has been done.

Figure 3 shows the cross-sectional structure of the basic cell 11, wiring area 1.
3 and the structure of the wiring layer. Second
The same symbols as in the figure indicate the same or equivalent items.

Elements such as transistors are formed on one surface side of the N-type substrate 30. The field oxide film 31 exists widely under the wiring region 13 and has a thickness of about 1 μm. There is a gate oxide film 40 under the gate electrode 22 of the transistor, and the film thickness is 500 to 1000 Å. There is a first insulating film 32 on the poly-Si wiring constituting the gate electrode 22, etc., and on this, the power supply wiring 26,
First wirings 35 and 36 made of 27 or Al are formed.
Here, the first wiring 35 connects within the logic blocks, and the first wiring 36 is provided in the wiring area and connects between the logic blocks. When it is necessary to connect the poly-Si wiring or the diffusion layers 20 and 21 to the first Al wiring, a contact hole 2 is formed in the first insulating film 32.
Open 3,24. A second insulating film 33 is formed on the first wiring, and second wirings 38 and 39 made of Al are further formed thereon so that the longitudinal direction thereof is orthogonal to the basic cell row. When it is necessary to connect the first wiring and the second wiring, a contact hole 37 is formed in the second insulating film 33.
open it. There is a third insulating film 34 on the top layer,
Protects transistors and wiring. In a general gate array LSI, contact holes 37 are provided in the first wiring, the second wiring, and the part necessary to connect the two.
In many cases, a desired LSI is obtained by changing the second insulating film 33 provided with . Also, the first wiring and poly
There is also an example in which the first insulating film 32, in which contact holes 23 and 24 are provided in areas necessary for connecting the Si wiring and the diffusion layer, is also changed.

In such a gate array, the wiring area 13 where the first wiring runs in the x-axis direction is fixed, and currently there are 10
There are about 30 pieces at intervals. However, when configuring an LSI, it is often a combination of random logic circuits and a group of registers that store data values. When a register group was constructed, most of the wiring area was wasted due to only running address lines and data lines, which was extremely uneconomical. As the number of gates increases as the scale of the LSI increases, the number of basic cell rows 42 aligned in the x direction also increases, as shown in FIG.
The wiring area 43 also increases. Therefore, as shown in FIG. 5, the proportion of the area of the wiring region in the area of the semiconductor chip increases, resulting in an increase in the size of the semiconductor chip.

Therefore, the present inventors proposed an improvement in Japanese Patent Application No. 56-66918. As shown in FIG. 6, elements 61 and 62, which are always used when forming a register group, are placed in the area between the basic cell rows 12, in the conventional wiring area, to increase mounting efficiency. In Fig. 6, 61 is two pairs of PMOS,
NMOS transistor, 62 is a pair of PMOS,
In the NMOS transistor, 60 is a poly-Si gate electrode. In the example of FIG. 6, a register as shown in FIG. 7 can be efficiently constructed. This will be explained below.
The register shown in FIG. 7 is a register circuit that utilizes the alternating high impedance dunk states of clocked inverters 70 and 71.

First, a clocked inverter will be explained with reference to FIG. When the clocked inverter 81 is shown by a PMOS transistor 82 and an NMOS transistor 83, it becomes as shown in FIG. 8b. Input 84 is PMOS,
It is input to NMOS transistors 82 and 83.
A control signal 86 is input to a PMOS transistor, and a control signal 87 having an inverted value thereof is generally input to an NMOS transistor.
When the control signal 86 is at a low level and the control signal 87 is at a high level, the MOS transistors to which the respective signals are input are turned on, so that the clocked inverter operates as a normal inverter. On the other hand, the control signal 86 is at High level and the control signal 87 is at High level.
When the level is low, the MOS transistors to which the respective signals are input are turned off, so the output signal 85 is in a high impedance state. 7th
Returning to the figure, this register circuit has a main body composed of clocked inverters 70, 71 and an inverter 72 shown in FIG. 7a, and is clocked by address signals 77, 78 shown in FIG. 7b. The control section includes a NAND gate 73 and an inverter 74 that control the states of inverters 70 and 71. When this register is selected, the address signals 77 and 78 are at a high level, so the control signal 75 is at a low level and the control signal 76 is at a high level. Therefore, clocked inverter 70 functions as a normal inverter, and the output of clocked inverter 71 becomes high impedance. Therefore, the same value appears at register output 80 as at input 79. When a register is not selected, one of the address signals 77 and 78 is at a low level, so the control signal 75 is at a high level and the control signal 76 is at a low level. Therefore, the output of clocked inverter 70 is in a high impedance state, and clocked inverter 71 works as an inverter. And clocked inverter 71
and an inverter 72 form a flip-flop to hold data. Since the main body of the register circuit shown in FIG. 7 requires 10 transistors, for example, 2.5 basic cells shown in FIG. 2 are required. Therefore, in the example shown in FIG. 6, between the basic cell rows 12, two pairs of PMOS, which are necessary for the control section configuration, are installed for every 2.5 basic cells.
NMOS transistor 61 and a pair of PMOS,
An NMOS transistor 62 is provided.

Although this is effective when configuring a register, there is a problem in that if a random logic circuit is configured using elements between basic cells, there will be a shortage of wiring channels.

An object of the present invention is to provide a semiconductor integrated circuit device suitable for a master slice type gate array LSI with high functional integration density, which can effectively utilize the area of a semiconductor chip and configure various circuits without impairing element utilization. There is something to do.

A feature of the present invention is that at least MOS transistors necessary for the configuration of logic gates are provided on a semiconductor substrate.
In a semiconductor integrated circuit device in which a plurality of basic cells each including a plurality of semiconductor elements each having a transistor are arranged, and a plurality of wiring layers are provided on the plurality of basic cells with an insulating layer interposed therebetween, the basic cell A plurality of these are arranged in one direction to form a basic cell column, and the basic cell column is arranged perpendicularly to the basic cell column so that the MOS transistors forming the logic gates between the adjacent basic cell columns face each other and have the same conductivity type. A plurality of wiring layers are arranged side by side in a direction, and the plurality of wiring layers are three or more wiring layers.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below with reference to drawings showing one embodiment of the invention.

First, FIG. 9a will be explained. Inside the semiconductor chip 10, a large number of first basic cells 92 are arranged in parallel in the x-axis direction to form a first basic cell row 94. Between each first basic cell row 94, a large number of second basic cells 93 are arranged in parallel in the x-axis direction.
This constitutes a basic cell column 95. The first basic cell row 94 and the second basic cell row 95 are arranged alternately in the y-axis direction without providing a wiring area, that is, in a spread-out manner.

FIG. 9b shows in detail the shaded area in FIG. 9a.

The basic cells 92 and 93 each include two PMOS transistors 90 whose sources or drains are connected in series, and two PMOS transistors whose sources or drains are connected in series.
A series of NMOS transistors 91 are arranged in parallel in the x-axis direction. The gate electrodes of the two series of PMOS transistors 90 and the gate electrodes of the two series of NMOS transistors 91 forming one basic cell 92 and 93 are respectively connected to a poly-Si common electrode 22.
Consists of. In addition, the gates of two PMOS transistors 90 and the two NMOS transistors 91
One of the gates may be configured with a common electrode, and the others may not be connected in common. Furthermore, they do not need to be connected by a common electrode.

Two basic cells 92 and 93 adjacent in the y-axis direction
The opposing MOS transistors are of the same conductivity type.

Each MOS transistor has poly-Si and a first layer.
Contact part 2 of Al wiring (hereinafter referred to as Al1 wiring)
3 and the contact part 24 between the diffusion layer and the Al wiring
is provided. A Vcc power line 26 is wired between the PMOS transistors 90 of the first basic cell row 94 and a second basic cell row 95, and a GND power wire 27 is wired between the NMOS transistors 91.

Next, a method of constructing a desired circuit block will be explained. Figure 10 shows the inverter 11 with Al1 wiring 35.
6,117, NAND gate 110,112,1
14, 120, NOR gate 111, 113, 1
15. This is an example in which a logic circuit block such as a latch circuit 118 is configured. Electrical connection is made by connecting the Al1 wiring (connection within the logic block circuit) 35 to the contact portion 23 between the poly-Si and Al1 wiring marked by white circles and the contact portion 24 between the diffusion layer and the Al1 wiring. be done. In addition, the Vcc power line 26 and
Since the GND power supply line 27 is formed of Al1 wiring, it is electrically connected by bringing the Al1 wiring 35 into contact with them.

FIG. 11 represents the various logic circuit blocks constructed in FIG. 10 using logic symbols. In addition, the input/output position 11 of the logic circuit block is shown in the figure.
9 is also shown. Also, the logical symbol 110 in the figure
The positions from 118 to 118 correspond to FIG.

Next, a method of connecting each logic circuit block will be explained using FIG. 12.

In Fig. 12, 39 is the second layer of Al wiring (hereinafter referred to as Al2 wiring) that is wired in the x-axis direction on the Al1 wiring via an insulating film, and 121 is the y Third layer of Al wired in the axial direction
wiring (hereinafter referred to as Al3 wiring).

For example, in the output section 122A of the two-input NAND gate 110, an Al3 wiring and an Al1 wiring are connected via an Al2 wiring. Run the Al3 wiring 121A in the y-axis direction from the output part 122A, connect it to the Al2 wiring 39A running in the x-axis direction at the point indicated by the x mark, and then connect it again to the Al2 wiring 39A running in the x-axis direction.
Connected to Al3 wiring 121B, inverter 116
input section 122B. Similarly, 2-input NAND
The output of latch 110 is also applied to control signal input 122C of latch 118.

The output of the inverter 116 is Al2 at the output section 37A.
It is connected to wiring 39B and input to another control signal input section 37B of latch 118. The data signal input section 122D of the latch 118 has two inputs.
The output of NOR111 is input. Latch 1
The 18 data output signals are input from the output section 122E to the 3-input NOR 113 and the 4-input NOR 115. This completes the register-related connections shown in FIG. 7. Furthermore, the output of the 4-input NOR 115 is input to the 2-input NAND 120.

As can be seen from FIG. 12, Al2 wiring 39 and Al3 wiring 121 are wired in the x-axis direction and the y-axis direction, respectively, on the elements used for logic operations.
Therefore, even though logic gates are arranged at high density, there is no shortage of wiring channels.

In order to further clarify the wiring method explained in FIG. 12, FIG. 13 shows the first and second basic cells 92, 93.
The cross-sectional structure and the structure of the wiring layer are developed and shown. The same reference numerals as in FIG. 3 indicate the same or equivalent parts. At the input/output position 119 of the logic circuit block, holes 23 and 24 are made in the first insulating film 32, and the Al1 wiring 35 and the poly-Si gate electrode 2 are connected through the holes.
2. Diffusion layers 20 and 21 are connected.

At the output part 37A of the inverter 116, a hole 37 is made in the second insulating film 33, and the Al1 wiring 35 and
It is connected to the Al2 wiring 39B. Since there is a second insulating layer 33 under the Al2 wiring 39, the Al2 wiring 39 can run over the element without electrically contacting it in areas where holes are not made.

In the output section 122A of the 2-input NAND 110, holes 37 and 140 are made at the same location in the second insulating film 33 and the third insulating film 34, and the Al2 wiring 39
The Al1 wiring 35 and the Al3 wiring 121 are connected via. A third insulating film 34 is provided under the Al3 wiring 121.
Al3 wiring 121 in places where holes cannot be made because of
has no electrical contact with either the Al2 wiring or the device. When connecting the Al2 wiring 39 and the Al3 wiring 121, it is sufficient to make a hole 140 in the third insulating film 34.

A fourth insulating film 142 is on the top layer and protects the transistors and wiring.

As you can see from the above explanation, at least
By changing the layers above the Al1 wiring for each user, the desired
You can get LSI.

According to this embodiment, by using three wiring layers, the conventional wiring area can be removed and basic cells can be placed in the conventional wiring area, so the arrangement density of basic cells can be significantly increased. can. Moreover, if the conventional wiring area is removed, each of the opposing two sets of basic cells 92 and 93 adjacent in the y-axis direction
Since the MOS transistors are of the same conductivity type, opposing PMOS transistors 90 and opposing NMOS transistors 91 share their respective P-well regions 25.
The distance between them can be shortened, and the arrangement density of basic cells can be further increased. Furthermore, since the two opposing MOS transistors of the basic cells 92 and 93 adjacent to each other in the y-axis direction are of the same conductivity type, the GND power supply line 27 connected to the NMOS transistor 91 and the Vcc connected to the PMOS transistor 90 It also becomes possible to use the power supply line 26 in common.

Furthermore, since the Al2 wiring 39 is wired in the x-axis direction and the Al3 wire 121 is wired in the y-axis direction, there is no shortage of wiring channels, and the arrangement density of basic cells and circuit blocks is improved.

In the embodiment of the present invention described above, two sets of
Although the explanation has been given by taking as an example a basic cell arrangement in which a PMOS transistor and two NMOS transistors are paired, the present invention can also be applied to three transistor pairs or variations thereof. The present invention can also be applied to processes other than CMOS.

Further, the present invention can be applied even if the Al2 wiring is wired in the y-axis direction and the Al3 wire is wired in the x-axis direction.

Generally, due to the manufacturing process, the width of Al3 wiring is thicker than that of Al2 wiring, so the direction of high wiring density is Al2 wiring.
It is preferable to use Al3 wiring in the direction where the wiring density is low.

As described above, according to the present invention, it is possible to obtain a semiconductor integrated circuit device suitable for a master slice type gate array LSI with high functional integration density.

[Brief explanation of drawings]

Figure 1 is a plan view showing the master method of a conventional gate array LSI, and Figure 2 is a plan view of a conventional gate array LSI.
3 is a cross-sectional view of a conventional gate array LSI and an expanded view showing the layer structure. FIGS. 4 and 5 are diagrams for explaining the increase in wiring area.
Figure 6 shows the gate array proposed earlier by the inventors.
A plan view showing the master system of LSI, FIG. 7 is a register circuit diagram, FIG. 8 is a circuit diagram for explaining FIG. 7, and FIG. 9 is a master system of gate array LSI showing an embodiment of the present invention. FIG. 10 is a block diagram of various logic circuit blocks constructed using an embodiment of the present invention, and FIG. 11 is a symbol diagram of various logic circuit blocks constructed using an embodiment of the present invention. , FIG. 12 is an explanatory diagram of a method of connecting various logic circuit blocks constructed using an embodiment of the present invention,
FIG. 13 is a gate array showing an embodiment of the present invention.
FIG. 3 is a cross-sectional view and a developed view showing the layer structure of the LSI. 10... Semiconductor chip, 92, 93... Basic cell,
35...Al1 wiring, 39...Al2 wiring, 121...Al3 wiring.

Claims (1)

[Scope of Claims] 1. A plurality of basic cells each consisting of a plurality of semiconductor elements each having at least a MOS transistor necessary for configuring a logic gate are arranged on a semiconductor substrate, and an insulating layer is placed on top of the plurality of basic cells. In a semiconductor integrated circuit device having multiple wiring layers via
A plurality of the basic cells are arranged in one direction to form a basic cell column, and the basic cell column is divided into basic cells such that MOS transistors forming logic gates between adjacent basic cell columns face each other and have the same conductivity type. A semiconductor integrated circuit device, characterized in that a plurality of wiring layers are arranged side by side in a direction perpendicular to a column, and the plurality of wiring layers are three or more wiring layers. 2. In claim 1, a power supply line is provided between the adjacent basic cell rows using one wiring layer among the three or more wiring layers, A semiconductor integrated circuit device characterized in that the power supply line is commonly used by MOS transistors. 3. In claim 1, the circuit has a desired function by connecting within the basic cell or between the basic cells using at least a predetermined first wiring layer of the three or more wiring layers. a second wiring layer constituting a block and formed on the first wiring layer with an insulating layer interposed therebetween; and a third wiring layer formed on the second wiring layer with an insulating layer interposed therebetween. A semiconductor integrated circuit device, characterized in that the circuit blocks are connected using at least one of the following.