JPH0252428B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a master slice semiconductor integrated circuit device, and particularly to an effective basic cell structure when a large number of memory structures are included.

In recent years, communication devices and computers have become increasingly integrated into ICs, and master slice LSIs are often used. Master slice type LSIs realize a circuit by regularly arranging transistors at predetermined positions and connecting the input and output terminals of each transistor by forming an aluminum conductive film in a predetermined grid. It is something. Generally, transistors are arranged throughout the chip by repeating structural units called basic cells. Further, from the viewpoint of operating speed, power consumption, and regularity of arrangement, so-called CMOS type transistors, which are complementary insulated gate field effect transistors, are used as transistors.

FIG. 1 shows an example of a plan view of a basic cell of a conventional CMOS type master slice type LSI.
That is, two of each are connected in series by the N type silicon substrate 1 and the P ⁺ source drain layer 6 and the N ⁺ source drain layer 3 formed on the P well layer 2 formed on the N type silicon substrate 1, respectively. of
PMOST 13 and NMOST 12 are formed with gate polysilicon 8, 5 and feedthrough polysilicon 9, and the respective source/drain layers 3, 6, gate polysilicon 5, 8, and feedthrough polysilicon 9 have contacts. It is shown that a hole 10 is drilled and wires are connected using an aluminum conductive film to form a circuit. The figure shows ^{an aluminum} conductive film 11A (i.e. V _DD
line), 11B (ie, Vss line) only.

This is shown in the simplified diagram of FIG. 1b, with the aid of which the structure can be explained.

Although conventional basic cells have a very effective structure for logic circuits, they have many structural problems when used for memory circuits. This will be explained using FIG. 2.

FIG. 2a shows a circuit diagram of a 1-bit static memory. Transfer gates T _G1 and T _G2 are normal
It is formed by an NMOS transistor, and bit line B and its inverted signal are applied to this input. The signal of the word line W is applied to the gate of the transfer gate, and the output of the transfer gate is
It is connected to the input of a flip-flop circuit consisting of CMOS inverters IA and IB. If we try to realize this circuit using a conventional basic cell, we will see three connections in the aluminum conductive film as shown in bold lines in Figure 2b.
1 basic cell, 12 transistors, 5 useless transistors 8A, 8A', 5A,
8C, 8C', 5C' are generated. This means that the cell utilization rate will drop to 7/12, or 5.8%.

In recent years, the number of gates in master slice type LSIs has increased, and the need to meet the internal memory requirements of IC devices has become increasingly important. However, conventional basic cells have the disadvantage that the cell utilization rate drops significantly when forming a memory.

An object of the present invention is to eliminate the conventional drawbacks by focusing on memory formation, and to provide a master slice semiconductor integrated circuit device including a basic cell that can configure both logic circuits and memory circuits without reducing cell utilization. There is a particular thing.

The present invention provides a master slice semiconductor integrated circuit device in which a plurality of basic cells each consisting of an element region and a wiring region are arranged regularly, and an aluminum conductive film is formed on a specified grid in the x and y directions. One of the second conductivity type transistors connected in series with the second conductivity type source drain layer formed on the type silicon substrate and the first conductivity type transistor connected in series with the first conductivity type source drain layer, one of which is four in number,
The other is constituted by a structure consisting of basic cells that exist in a relationship to form a set of complementary transistors with at least one of the two central transistors.

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 3, the first embodiment of the present invention has gate polysilicon 8 of two PMOS transistors connected in series by a P ⁺ source/drain layer 6 on an N type silicon substrate 1, and an ^N It is formed by the gate polysilicon 5 of four NMOS transistors connected in series by the source/drain layer 3, the gate polysilicon 5, 8, and the contact hole 10 of the source/drain layer 6, 3.

FIG. 4 shows an aluminum conductive film pattern (indicated by a solid line) showing one bit of the static memory cell shown in FIG. 2a according to the first embodiment of the present invention.
This is what is shown. In the figure, gate polysilicon 5
A is the gate of TG ₁ , 5D is the gate of TG ₂ ,
Gate polysilicon 5B and 8A constitute IB, and gate polysilicon 5C and 8B constitute IA. As shown in the figure, the cell utilization rate for memory configuration is
It is 100%. As can be seen by comparing the first embodiment of the present invention shown in FIG. 3 with the conventional example shown in FIG. There is no problem.

FIG. 5 shows two inputs in the first embodiment of the present invention.
NOR circuit implementation example a and 2-input NAND circuit implementation example b
shows. In FIG. 5a, gate polysilicon 5
Since A and 5D are open, this gate polysilicon can be used as a feed through. If you simply consider the transistor part, the first
In the conventional case shown in the figure, the cell utilization rate is 100%, and in the example of the present invention, it is 4/6, or 67%, which is higher than 58%, which is an example of realizing the memory circuit in the conventional case.
Since the feed-through polysilicon 9 shown in the figure is unnecessary in the present invention, the overall cell utilization rate and the degree of integration of basic cells can be improved over the conventional case.

FIG. 5b shows an implementation example of a two-input NAND circuit.
Originally, it was determined by a wiring similar to that shown in Figure 5a, but 2
An example of an improvement in which the logic level is lowered by effectively using the extra NMOST is shown below. In the conventional case, the output V ₀ and
There are two series NMOSTs between VSS, but in the present invention two parallel NMOSTs are connected in series.

FIG. 6a shows a second embodiment of the present invention, in which two gate polysilicon 58 in the center are connected, and the gate polysilicon of NMOST at the left and right ends can also be used as feed-through polysilicon. An example is shown below.

FIG. 6b shows a third embodiment of the invention,
A basic cell with 2 NMOSTs and 4 PMOSTs,
A case is shown in which basic cells with two PMOSTs and four NMOSTs coexist. This case is characterized in that the cell utilization rate when forming logic cells is much higher than in the first embodiment of the present invention. However, both gates TG ₁ and TG ₂ in Fig. 2a are NMOST.
Although there is a drawback that the PMOST case and the PMOST case coexist, there is no problem with the circuit.

As explained above, in a master slice type LSI, the present invention has a structure in which two series PMOSTs and four series NMOSTs are assembled with complementary transistors, so that they can be used as either memory circuits or logic circuits. This also has the effect of increasing the cell utilization rate.

[Brief explanation of drawings]

Figures 1a and b are diagrams showing the basic cell of the conventional CMOS type master slice system. Figure 1a is a plan view, Figure 1b is a simplified diagram, and Figures 2a and b are static memory circuits. In the figures, Fig. 2a is a circuit diagram, Fig. 2b is an example realized using the conventional basic cell shown in Fig. 1, Fig. 3 is a simplified diagram showing the first embodiment of the present invention, and Fig. 4 1 is a diagram showing an example of a static memory circuit in a basic cell according to the first embodiment of the present invention,
5a and 5b are examples of realizing a logic circuit according to the first embodiment of the present invention, and FIG. 5a is an example of a 2-input NOR circuit.
Figure 5b is an example of an improved two-input NAND circuit.
FIG. 6a is a simplified diagram showing a second embodiment of the invention;
FIG. 6b shows a third embodiment of the invention. In the figure, 1...N-type silicon substrate, 2
...P well layer, 3...N ⁺ source, drain layer,
4...P ⁺ sub-layer, 5...NMOST gate polysilicon layer, 6...P ⁺ source/drain layer, 7
. . . N ⁺ sub-layer, 8 . . . PMOST gate polysilicon layer, 9 . . . Feed-through polysilicon layer, 10 . . . Contact hole, 11 .
PMOST region, 58...NMOST, PMOST common gate polysilicon layer.

Claims (1)

[Claims] 1 a plurality of second conductivity type transistor groups in which a plurality of second conductivity type source/drain layers formed in a first conductivity type semiconductor substrate are connected in series; and a second conductivity type transistor group in the first conductivity type semiconductor substrate; In the master slice semiconductor integrated circuit in which basic cells including a plurality of first conductivity type transistor groups in which a plurality of first conductivity type source drain layers formed in a well layer are connected in series are regularly arranged, A first transistor group whose basic cells include four transistors of one conductivity type of the first conductivity type and the second conductivity type, and two transistors of the other conductivity type of the first conductivity type and the second conductivity type. and a second transistor group consisting of transistors of the same type, and the gate electrodes of the two central transistors of the first transistor group are arranged in a straight line so as to form a complementary circuit with the second transistor group. A master slice semiconductor integrated circuit device, characterized in that it is formed on a master slice semiconductor integrated circuit device.