JPH0373012B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a program/trace accumulation/recording device, and particularly to a program/trace storage/recording device that enables real-time data transfer to an external storage device that enables maximum tracing with minimum tracing memory capacity. This invention relates to a program trace accumulation recording method for accumulating trace data.

Conventionally, in dynamic structure tracing of a program in an information processing device that has a micro program control method or a micro computer program method, tracing must be stopped when the trace memory prepared in advance becomes full. First, there has been a problem in that the faster the information processing apparatus operates, the larger the trace memory capacity required to record continuous program operations.

To solve this problem, a method has been proposed in which the trace data automatically wraps around when it exceeds the memory capacity, but when this method is used, only a part of the traced program can be traced. Otherwise, the problem of losing necessary trace data occurred, and this method could not be said to be satisfactory.

SUMMARY OF THE INVENTION An object of the present invention is to provide a program/trace data storage/recording device that solves these conventional problems and enables virtually infinite tracing with a minimum trace memory capacity.

In order to achieve the above object, the program trace storage and recording device according to the present invention is a storage and recording device for trace data of a program in an information processing device having micro program control or a micro computer program. A trace control circuit (trace control circuit 21 in FIG. 1) for tracing the operation of the program in the information processing device 10) in FIG. 1, and for accumulating trace data discriminated by the trace control circuit. A plurality of trace memory banks divided into banks (trace memory banks 22a and 22b in FIG. 1), a trace memory bank control circuit (trace memory banks 22a and 22b in FIG. 1) that controls reading and writing of the trace memory banks (trace memory banks 22a and 22b in FIG. a memory bank control circuit 23), an external storage device (external storage device 24 in FIG. 1) for storing data when the data is traced in excess of the capacity of the tracing memory bank, and the external storage device an external storage device control circuit (external storage device control circuit 25 in FIG. 1) that controls the external storage device, and a memory bank control circuit for external storage device output that temporarily stores the data to be transferred to the external storage device (external storage device control circuit 25 in FIG. 1). A memory bank control circuit 26) for outputting an external storage device is provided, and the capacity of the trace memory bank is set to store trace data for the time required to transfer the data in the trace memory bank to the external storage device. First, trace data is sequentially recorded in one trace memory bank (bank 22a in Figure 1) to have enough capacity, and when it becomes full with recorded trace data, the memory bank is switched. , starts transferring the data recorded in the trace memory bank (memory bank 22a in FIG. 1) to the external storage device via the external storage device output memory control circuit and the external storage device control circuit. The next trace memory bank (memory bank 22b in Figure 1) is
It is characterized by the start of data recording.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

Section 1 is a functional block diagram showing a program trace storage and recording device from an information processing device, which is an embodiment of the present invention.

In the figure, 10 is an information processing device, and 20 is a program trace storage recording device. Also, 2
1 is a trace control circuit, 22a and 22b are two banks of trace memory 22, 23 is a trace memory bank control circuit, 24 is an external storage device,
25 is a control circuit for the external storage device, and 26 is a memory bank control circuit for outputting the external storage device.

The operation of the above embodiment device will be explained below.

Output information from the information processing device 10 (trace/
data) is program trace storage recording device 2
It is discriminated by the trace control circuit 21 of No. 0 and sent to the trace memory bank control circuit 23 via the interface 31.

In this way, the trace control circuit 21 controls the output (address bus, data bus information) from the information processing device 10 to be sent as trace information to the trace memory bank control circuit 23. In this case, there are two types of program operation records: a record of all passed addresses focusing on execution addresses, and a record of instruction addresses/branch instruction codes/branch destination addresses focusing on branch operations. For this recording, the instruction address and instruction code are collected, branch instruction determination control is performed, and in the case of a branch instruction, the branch address is collected. To record the execution address, the tracing memory bank control circuit 23 records the passing address of the execution program in the information processing device 10 in correspondence with the memory address of the tracing memory bank 22. This record is processed entirely within the trace memory bank and is not transferred to an external storage device. The contents of the branch operation record include an instruction address, an instruction code, and a branch destination address, and are recorded in the trace memory bank 22 by the trace memory bank control device 23 each time an event occurs. This control also includes control for suppressing duplicate tracing due to program loops in execution state recording. Note that discrimination is one of the processes of the trace control circuit 21 that is performed by the information processing device 1.
0 (advice, data bus information) and formatting it as trace information (for example, see the address flag format described in Japanese Patent Laid-Open No. 53-54440).

The trace memory bank control circuit 23 selects one of the two banks of the trace memory 22 (for example, banks 1 and 22a).
Then, trace data is sent via the interface 32 and recorded. When the above-mentioned selected trace memory bank 22a becomes full, that is, the trace memory bank control circuit 23 indicates the bank number of the trace memory bank 22 and the final address at which trace data can be stored in the memory bank. , a final event storage address, and a current event storage address for sequentially storing the trace data sent from the trace control circuit 21. By comparing the final event storage address and the current event storage address, the memory bank If it is determined that it is full, the trace memory bank control circuit 23 switches the trace memory bank (in this case, bank 2, 22b) and at the same time,
Via the interface 34, a request is made to the external storage device control circuit 25 to output trace data to the external storage device 24. Furthermore, the trace memory bank control circuit 23
5, the external storage device output memory bank control circuit 26 is informed of the bank number (in this case, bank 1, 22a) of the trace memory 22 to be coupled and coupled to the external storage device 24.

Tracing performed in real time with the information processing device 10 is hindered when outputting from the tracing memory bank 22 to the external storage device 24, so as a countermeasure, the contents of the tracing memory 22 are output to the external storage device 24. The external storage device output memory bank control circuit 26 outputs the external storage device 24 based on the trace memory 226 bank number received from the trace memory bank control circuit 23.
selection of the trace memory bank 22 to be output to;
Control switching.

The external storage device circuit 25 is connected to the interface 3
6 is transferred to the external storage device 24 via the interface 37 and stored therein.

During this time, the output information (trace data) from the information processing device 10 is stored in the trace memory bank that is not connected to the external storage device control circuit 25 by the trace control circuit 21, trace memory bank control circuit 23, etc. ing.

In the device of the above embodiment, the trace memory 22 has a two-sided configuration of bank 1 and bank 2, but more banks are provided and these are connected to the trace memory bank control circuit 23 and the external storage device output memory. It may be configured to be controlled by the bank control circuit 26.

Note that the capacity of the trace memory 22 is determined based on the time required to transfer the data in the memory 22 to the external storage device 24, and the capacity to store the trace data from the information processing device 10 during that time. The necessary capacity shall be secured. In other words, a capacity is required that balances the time for outputting the contents of the tracing memory 22 to the external storage device 24 and the time for tracing from the information processing device 10 with respect to the memory capacity.

Furthermore, in this embodiment, since the performance of the information processing device is higher than that of the external storage device, the information is first stored in a memory that can handle high speeds, and then transferred to the external storage device at a certain timing.

The capacity of the trace memory 22 is determined by calculating the program execution step at which the frequency of occurrence of branch instructions to be traced in the information processing device 10 is an average value. On the other hand, the transfer speed to the external storage device (external storage device performance) is the time required for the trace data to be completely written to the surface of the trace memory bank ((trace memory bank capacity ÷ event trace data length)) × (average branch instruction generation interval + branch instruction execution time)). As a measure to prevent output information from being destroyed in the external storage device due to memory bank switching when the appearance frequency of trace target instructions exceeds the average value, the trace control circuit has a function of temporarily suppressing the operation of the information processing device 10. 21.

As described above, according to the present invention, in a storage storage device for storing trace data of a program in an information processing device having a micro program control method or a micro computer program method, the operation of the program in the information processing device is provided. A trace control circuit for tracing, a plurality of trace memory banks, a trace memory bank control circuit, an external storage device, an external storage device control circuit, and a memory bank control circuit for outputting the external storage device are provided. The capacity of the trace memory is set to be enough to transfer the data in the memory to the external storage device, and when the trace memory becomes full, the data in the trace memory is transferred to the external storage device output memory. Since the trace data is transferred and stored to the external storage device via the control circuit and the external storage device control circuit, the trace memory itself can be kept to the minimum capacity while still being able to store large amounts of trace data. It becomes possible to accumulate and record in real time.
As a result, it is possible to continuously trace a large-scale program, and there is no fear that necessary information cannot be traced or is lost, unlike in the past.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of a program trace storage and recording device according to an embodiment of the present invention. 10: Information processing device, 20: Program trace storage recording device, 21: Trace control circuit, 2
2: Trace memory, 23: Trace memory bank control circuit, 24: External storage device, 25: External storage device control circuit, 26: External storage device output memory control circuit.

Claims (1)

[Claims] 1 Micro program control or micro program control
In a storage recording device for trace data of a program within an information processing device that controls a computer program, a trace control circuit for tracing the operation of the program within the information processing device; a plurality of trace memory banks divided into banks for storage; a trace memory bank control circuit connected between the trace memory bank and the trace control circuit and controlling reading and writing of the trace memory bank; an external storage device for storing data when tracing data exceeds the capacity of the tracing memory bank;
an external storage device control circuit that is connected between the external storage device and the trace memory bank control circuit and that controls the external storage device; and a control circuit that connects the external storage device control circuit and the trace memory bank control circuit. An external storage device output memory bank control circuit is provided which is connected between the trace memory bank and controls the switching of data from the trace memory bank. First, trace data is sequentially recorded in one trace memory bank until it becomes full with the recorded trace data, in order to have enough capacity to store trace data for the time required to transfer it to an external storage device. At the same time, switching the memory bank and starting to transfer the data recorded in the trace memory bank to the external storage device via the external storage device output memory bank control circuit and the external storage device control circuit, A program/trace storage/recording device characterized in that it starts recording subsequent trace data in another trace memory bank.