JPH037404A - Chip type delay line - Google Patents

Abstract

PURPOSE:To manufacture a delay line with small size and suitable for high density mount by stacking a desired number of sets of a circuit board and a dielectric board of the same shape in pairs and and stacking a connection board and an electrode board on and under the circuit board and the dielectric board so as to form a chip. CONSTITUTION:A circuit board A comprising a rectangular green sheet (unburned ceramic board) 10 on the surface of which a zigzag strip line 11 is printed and on the rear side of which a ground conductor 12 is fully printed and a dielectric board B comprising only the green sheet 10 are formed as a unit. Three units are stacked in this embodiment, and a connection board C forming a frame is stacked to the uppermost unit and an electrode board D is stacked to the lowermost unit. Then a delay line having an optional delay time is easily obtained.

Description

[Detailed Description of the Invention] [Summary] Regarding delay lines used in high-frequency circuits of optical transmission equipment, particularly regarding the structure of the delay line incorporated in a chip, workability and reliability are improved, and - The purpose is to provide a chip-type delay line structure suitable for high-density mounting.The circuit board consists of a rectangular green sheet with a strip line printed on the front side and a ground conductor on the back side, and a green sheet only. A predetermined number of units consisting of two dielectric substrates are stacked, a connection board is placed on the top layer, an electrode substrate is placed on the bottom layer, and these are integrally fired.

[Industrial application field]

The present invention relates to a delay line used in a high frequency circuit of an optical transmission device, and more particularly to the structure of a delay line built into a chip.

[Conventional technology]

In recent years, as optical transmission devices have become more densely packaged, each element has been required to be smaller and more highly integrated.

Conventionally, delay circuit elements used in high-frequency circuits of optical transmission equipment are made of two back-to-back strips with strip lines 2 running in a zigzag pattern on one side of a substrate 1, as shown in Figure 6. It had a so-called SIP type structure in which the IJ tube lines 2 were connected to each other to form a delay line of a desired length.

[Problem to be solved by the invention]

The elements of this SIP type structure are large in shape and do not correspond to the recent trend of high-density packaging, and also
Since the connection between the IJ tube line 2 and the terminal 3 relies on soldering, there are drawbacks of low workability and lack of reliability.

SUMMARY OF THE INVENTION In view of the problems of the prior art, it is an object of the present invention to provide a chip-type delay line structure that has improved workability and reliability and is suitable for high-density packaging.

[Means to solve the problem]

The purpose of this is to laminate a predetermined number of units consisting of two circuit boards: a circuit board made of a rectangular green sheet with a strip line printed on the front side and a ground conductor printed on the back side, and a dielectric board made of only the green sheet. However, this is achieved by a chip-type delay line structure characterized in that a connection board is placed on the top stage, an electrode board is placed on the bottom stage, and these are integrally fired.

[For production]

By combining a circuit board and a dielectric board,
A delay line having an arbitrary delay time can be easily obtained by stacking a desired number of LC circuit units and connecting the strip lines to each other.

Hereinafter, the present invention will be explained in more detail based on preferred embodiments shown in the drawings.

〔Example〕

FIG. 1 is a perspective view of an example of a chip-type delay line according to the present invention, and FIG. 2 is a side view of the chip-type delay line exploded into its constituent elements.

A zigzag strip line 11 is formed on the surface of a rectangular green sheet (unfired ceramic substrate) 10.
A circuit board A having a ground conductor 12 printed thereon and a ground conductor 12 printed on the back side thereof, and a dielectric board B consisting only of a green sheet 10 constitute a pair of units. In the illustrated embodiment, three units are stacked, with a frame-shaped connection board C being stacked at the top and an electrode board at the bottom.

As shown in FIGS. 3(a) and 3(b), the circuit board A has a connection pattern 14 connected to each end of the strip line 11 at approximately the center of its pair of opposing sides s and t. .14°, and another connection pattern 13 is provided on the side surface S at a position apart from the connection pattern 14. Further, as shown in FIG. 4(a), the mutually opposing side surfaces u and v of the dielectric substrate B
A connection pattern 14 of the circuit board A is provided on one side U of the circuit board A.
A connection pattern 15 is provided at a central position corresponding to . An independent connection pattern 16 is provided at a certain distance from the position of the connection pattern 15.

Further, on the side surface V opposite to the side surface U, an independent connection pattern 16'' is provided at a position centrally symmetrical to the connection pattern 16.

Therefore, when circuit board A and dielectric board B are stacked, as shown in FIG. A conductive path is formed that connects to the connection pattern 15 on the side surface U of the substrate B.

This conduction path reaches the connection pattern 14° on the side of the circuit board A of the second unit to be laminated next via this connection pattern 15, and is connected to the strip line 11 on the side of the opposite side S. A connection pattern 14 is reached.

Then, it reaches the connection pattern 15 on the side surface U of the dielectric substrate B that comes into contact with this. Here, the dielectric substrate B has the same shape as the dielectric substrate B of the unit stacked above, but the phase is rotated by 180 degrees within the same plane as shown in FIG. 4(b). It is layered.

In this way, every other dielectric substrate B has a phase of 18
By stacking a desired number (three sets in this example) of units while rotating them by 0°, one conductive path is sequentially formed up to the lowest electrode substrate.

As shown in FIG. 4(d), an electrode 17 is provided on the opposite side surfaces w and x of the electrode substrate to contact the connection pattern 15 of the dielectric substrate B on the W side. An electrode 18 is provided at X to contact the connection pattern 16°. This electrode 18 is connected to the connection pattern 16 or 16'' of the dielectric substrate B and the connection pattern 13 of the circuit board A.
and the top connection board C via route ① in Figure 5.
(See FIG. 4(c)). This finishing connection pattern 19 is configured to be in contact with the connection pattern 14 on the side surface S of the circuit board A of the first unit, so that the strip lines 11 of each unit are connected in series and the picture electrode 17 , 18 are formed.

Incidentally, on the other sides p and r of each board A to D where no connection pattern is provided, a ground connection pattern 20 connected to the ground conductor 12 on the back surface of the circuit board A is provided, and each board is When stacked, they are each electrically connected and are completely grounded by the ground electrode 21 on the electrode substrate.

A desired number of units consisting of these substrates A and B made of green sheets are stacked, and further substrates C and D are placed above and below them.
A chip-type delay line that can achieve any desired delay time can be obtained by baking and integrating the laminated layers using a known method.

〔Effect of the invention〕

According to the present invention, the circuit boards A each have the same form.
and dielectric substrate B are laminated in a desired number,
Since the chip is formed by laminating the connection substrate C and the electrode substrate above and below, it becomes possible to easily manufacture a small-sized delay line suitable for high-density packaging.

[Brief explanation of the drawing]

Figure 1 is a perspective view of a chip-type delay line according to the present invention, Figure 2 is an exploded side view, and Figures 3 (a) and (b) are front and back views showing the pattern of the circuit board. , Figures 4(a) to (d) are plan views showing patterns of other boards, Figure 5 is a developed diagram of the circuit when each board is laminated, and Figure 6 is a conventional SIP type. FIG. 3 is a perspective view of a delay line. 10... Green sheet, 11... Strip line, 12... Earth conductor, 14, 14', 15. 16. 16'...
・Connection pattern, 17.18... Input/output electrode, 19... Finished connection pattern, 20... Earth JH [pattern, A... Circuit board, B... Dielectric substrate, C... Connection board, D...electrode board.

Claims (1)

[Claims] 1. A circuit board (A) consisting of a rectangular green sheet (10) with a strip line (11) printed on the front side and a ground conductor (12) on the back side, and a dielectric substrate (B) consisting of only the green sheet (10). ) are stacked in a predetermined number, a connection board (C) is placed on the top layer, an electrode substrate (D) is placed on the bottom layer, and these are fired as one unit. Chip type delay line.