JPH0374969B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a Josephson master flip-flop, and in particular to a Josephson master flip-flop with a wide operating margin suitable for application to an AC-driven Josephson LSI. Regarding.

[Background of the invention]

Consists of logic elements that perform latching operations
In an AC-driven Josephson logic circuit system, it is necessary to reset the logic element by returning the gate current to zero every cycle. Therefore, a flip-flop circuit is required that stores data obtained by the logic network in one cycle and transfers the data to the logic network again in the next cycle. This flip-flop circuit consists of a master flip-flop that stores data during the inactive time within one cycle, and a slave flip-flop that reads data from the master circuit at the beginning of the active time of the next cycle and holds the data during that cycle. It consists of A typical example of such flip-flops is the one described in the IEEE Journal of Solid-State Circuits.
Volume 17 No. 6 December 1982 Pages 1201-1210-1210
(hereinafter referred to as Document (1)). FIG. 1 shows the structure of the master flip-flop described in the same document (FIG. 2). In the figure, 101 is a 2-input OR-AND gate, 102 is a write gate, 103 is a detection gate,
104 and 105 are two-input OR gates that make up 101, and 106 is a two-input OR gate that also makes up 101.
It is an AND gate. 111 is a write enable input (I _w ), 112 is a data input, 113 is an AC power supply (V _AC ), 114 is a drive input to the write gate (I _D ),
121 is a load resistance (R _L ), 112 and 123 are coupling resistances (R _S ), 124 is a power supply resistance (R _P ), 107
is a storage loop in which persistent current 115 (I _L ) is stored.

Now, in general, the load resistance R _L of a Josephson theoretical gate with a critical current I _n is given by IEEE Journal of Solid-State Circuits, Vol.
As described in Volume 14, No. 5, October 1979, pages 787 to 793 (hereinafter referred to as Document (2)), the output voltage V _O is set to be equal to or less than the gap voltage V _g . FIG. 2 shows the current-voltage characteristics of the Josephson device described in FIG. 1(d) of the same document. In the example inserted in the same figure, 201
is a Josephson device, and 202 is a load resistance. In FIG. 2, the position where the current-voltage characteristic of the Josefson device intersects with the load straight line with slope R _L ^-1 is the operating point of the output voltage V _O. R _L is selected so that V _O <V _g so that the output current I _RL can be large.

In fact, in Reference [1], the load resistance R _L 121 shown in Fig. 1 is designed to be 10 to 16 Ω (13 ± 3 Ω), and V _O = I _g = 0.2 mA, V _g = 2.8 mV. I _g R _L = 0.2 x 13 = 2.6 mV < V _g . If the load resistance R _L 121 is selected in this way, the output current I _RL will naturally change in proportion to the gate current I _g . In Figure 1, the power supply resistance R _p 124 is 73Ω, which is considered to be the standard value.
choose. Since the critical currents I _n of the gates 102 to 106 are equally 0.2 mA, the magnitude of the power supply 113 (V _AC ) can be set to a maximum of V _AC =I _n R _p =0.2 x 73 = 14.6 mV. Taking this value as 100%, the gate current margin is an important indicator of the range of V _AC in which the entire flip-flop operates. Here, the ratio of the power supply voltage to the maximum power supply voltage of the power supply 113 is referred to as the bias ratio of V _AC . FIG. 3 shows how the drive input _ID to the write gate of the circuit of FIG. 1 changes with the bias rate of V _AC . Coupling resistance R _S 1
12 and R _L 123 are the central design values 11 and R L 123, respectively.
It was set to 13Ω. When the bias rate of V _AC is close to 100%, I _D is saturated at 104 and 105.
This is because the operating point of the gate falls within the constant voltage region (the region where V _O =V _g ). The critical current I _n of the write gate 102 is shown as a function I _n (I _w ) of the write enable input I _w in FIG. 6(b) of document [2], which is reproduced in FIG. 4. Not all of the current _ID becomes I _L 114, but some amount remains as the gate current of write gate 102. This residual amount is constantly quantized and has a value less than or equal to I _n (I _w ).
When writing '1' to the storage loop 107, the write enable input I _w falls between the valleys of the threshold characteristics (the fourth
401), the residual gate current 102 has a value less than I _FLOOR in the figure. This value is said to be approximately 50μA, and is shown in Figure 3.
The value obtained by subtracting a value of 50 μA or less from I _D is the current value stored in the storage loop. Since the residual gate current shows stochastic changes depending on the initial conditions, even if the resistors R _S 122, 123 and R _L 121 are the central design values, the value of I _L corresponding to '1' will fall within the range shown in Figure 5. It will be distributed. On the other hand, detection gate 1
03 also has threshold characteristics similar to those in Fig. 4, and I _L
Unless it falls within this valley, it cannot be detected as a '1' level. This valley is said to be in the range of I _L = 90 to 160 μA, and stable detection of '1' under any initial conditions is possible only when V _AC is biased to 75% or more. It will be done.
If the bias margin for the gate current is narrow in this way, the operation tends to become unstable.

[Purpose of the invention]

The purpose of the present invention is to ensure that the '1' level storage current of the storage loop falls within a certain range within a sufficiently wide range of gate current bias ratios, so that the main body of the flip-flop circuit has a wide bias margin with respect to the gate current. Josephson master flip-flops.

[Summary of the invention]

If the operating point of the Josephson logic gate is in the constant voltage region, the output current of the Josephson logic gate will be a constant value determined by (gap voltage)/(load resistance). Therefore, as is well known, by setting the critical current of the Josephson device sufficiently large relative to the load resistance and driving the gate with a sufficiently large gate current, the output current can be adjusted to bias fluctuations. It can be set to a constant value regardless of the The present invention applies this principle to the Josephson master flip-flop.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described using FIG. 6. This figure shows the structure of a master flip-flop according to the present invention, in which the critical current values of gates 604, 605, and 606 are
The only difference from FIG. 1 is that the resistance values of the power supply resistors 624, 625 are smaller than those of the power supply resistors 124, 125 in inverse proportion to the power supply resistors 04, 105, and 106. gate 60
The critical current value of 4,605,606 is gate 10
It is 1.5 times 4,105,106, and the power supply resistance is 6
The resistance value of 24,625 is the power supply resistance 124,125
We will deal with the case where it is 2/3 times as large. Other resistance values are the same as in FIG. In this case, the magnitude of the ``1'' level persistent current I _L stored in the storage loop is determined as shown in FIG. 8 using the same procedure as in FIG. 5. From the same figure, in order to stably detect '1' at the detection gate, the voltage value of AC power supply V _AC must be 55%.
Anything above that is fine.

In addition, in the discussion up to now, write enable input I _w 1
It is assumed that the value of 11 falls in the valley of the threshold curve of the write gate 102 (401 in FIG. 4), but this also requires the same attention as in the case of _ID . Output obtained from a normal two-input OR gate (critical current I _n (0) = 0.2 mA with no input) powered by a standard 73 Ω supply resistor with a write enable input I _w through a 12 Ω load resistor. Let it be a current. In this case I _w
Figure 9(a) shows the change with respect to V _AC . The write enable input _Iw falls within the valley of the write gate threshold curve in the bias rate range of 51% to 100%. On the other hand, the write enable input _Iw obtained through a load resistance of 19Ω from a 2-input OR gate with 2/3 times the power supply resistance and 3/2 times the critical current is as shown in Figure 9 (b). . The write enable input I _w falls into the valley of the write gate threshold curve at a bias rate of 42% ~
It can be seen that the range is 100%. That is, it is effective to supply the write enable input I _w from the gate with a large critical current.

As described above, by increasing the ratio of the critical current of the gate that generates the drive input _ID and write enable input _Iw to the write gate and the critical current of the write gate and detection gate, the master flip-flop output Although it has been shown that the matching between _L and the slave flip-flop input stage can be improved, this does not mean that it is better to make this ratio as large as possible. The output of a slave flip-flop or ordinary combinational logic circuit,
The reduction in gate compatibility with increased critical current must also be considered. In a two-input OR gate, if the critical current I _n is increased, the LI _n of the device increases.
This is because the input margin decreases as the product increases. Figure 10 shows (a) when the critical current of the gate that generates the write enable input I _w and the drive input _ID is increased by α times compared to other gates.
(b) the lower limit of the bias range that allows matching between the master flip-flop output and the slave flip-flop input stage; and (b) the input of the gate that generates the normal logic circuit output and write enable input I _w and drive input I _D. An example of the lower limit of the bias range that can be matched with the stage is shown. In this example, even if α is increased beyond 1.6, the margin of the entire flip-flop cannot be improved. The optimal value of α depends on the selection of device inductance, coupling resistance between circuits, output resistance, power supply resistance, etc., but is generally within 2.

〔Effect of the invention〕

As described above, according to the present invention, the '1' level storage current of the storage loop falls within a certain range within a sufficiently wide range of gate current bias ratios, and the output of the master flip-flop and the input stage of the slave flip-flop are The flip-flop can now be matched over a wide range of bias ratios, and the entire flip-flop can operate over a wide range of gate current bias ratios.

[Brief explanation of drawings]

Figure 1 shows the conventional structure of a master flip-flop, Figure 2 shows how to set the load resistance of the logic gate, and Figure 3 shows the two-input OR-AND gate output current in the conventional structure. Figure 4 shows the bias rate dependence, Figure 4 shows the threshold characteristics of the write gate, Figure 5 shows the '1' stored in the storage loop.
6 is a diagram showing a different part from the conventional master flip-flop according to the present invention. FIG. 7 is a diagram showing a method of setting the load resistance of a logic gate. Figure 8 is a diagram showing the distribution range of the persistent current at the '1' level stored in the storage loop in the master flip-flop according to the present invention, and Figure 9 is a diagram showing the bias rate dependence of the output current of the two-input OR gate. Figure 10 shows the range of bias ratios that can be matched at the connections between each circuit when the critical current of the gate that generates the write enable input and I _w drive input I _D is increased by α times compared to other gates. Diagram showing. Explanation of symbols, 101...2 input OR-AND gate, 102...Write gate, 103...Detection gate, 104, 105, 604, 605...2 input
OR gate, 105,606...2 input AND gate, 111...Write enable input, 112...
Data input, 113... AC power supply, 114... Drive input to write gate, 121... Load resistance, 122, 123... Coupling resistance, 124, 12
5,624,625...Power supply resistance, 107...Storage loop, 115...Persistent current accumulated in 107.

Claims (1)

[Claims] 1 A superconducting loop consisting of a write gate made of a Josephson device and an inductance provided in parallel with the write gate, and a drive input to the write gate and a write enable input for the write gate. , and a driving gate consisting of a Josephson device, in which the persistent current stored in the superconducting loop is varied by switching the write gate,
JOSEPH, characterized in that the critical current value of the drive gate is set to a larger ratio than the critical current values of the write gate and other gates, and the power supply resistance connected to the drive gate is reduced by the reciprocal of the ratio. Song Master Flip Flop.