JPH03753Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field The present invention relates to a reactance circuit integrated into an integrated circuit, and particularly to a reactance circuit with improved frequency characteristics. (b) Prior Art As shown in Japanese Unexamined Patent Publication No. 59-57515, a method of constructing an equivalent reactance using a semiconductor integrated circuit is known. FIG. 2 shows the reactance circuit described in the above publication, in which 1 indicates first and second transistors 2 whose emitters are commonly connected.
and 3, and the first and second transistors 2 and 3
a variable current source 4 connected to a common emitter of the transistors, a resistor 5 connected between the bases of the first and second transistors 2 and 3, and a resistor 5 connected to the common emitter of the second transistor 3;
capacitor 6 connected between the base and collector of
and a current inversion circuit 7 connected between the collectors of the first and second transistors 2 and 3, and as a positive equivalent reactance when viewed from the input terminal 8 connected to the collector of the second transistor 3. a first reactance circuit that operates; 9 ; third and fourth transistors 10 and 11 whose emitters are commonly connected; and a variable current source 12 which is connected to the common emitters of the third and fourth transistors 10 and 11; the third and fourth transistors 1
a resistor 13 connected between the bases of 0 and 11;
It consists of a capacitor 14 connected between the base and collector of the third transistor 10, and a current inversion circuit 15 connected between the collectors of the third and fourth transistors 10 and 11. This is a second reactance circuit that operates as a negative equivalent reactance when viewed from the input terminal 8 connected to the second reactance circuit. Therefore, the reactance X ₁ of the first reactance circuit 1 that operates as a positive reactance is: X ₁ = Gm ₁ C ₁ R ₁ ...(1) [However, Gm ₁ is The mutual conductance R ₁ of the differential amplifier section consisting of is the resistance value of the resistor 5, and C ₁ is the capacitance value of the capacitor 6], and the reactance X ₂ of the second reactance circuit 9 , which operates as a negative reactance, is X ₂ = -Gm ₂ C ₂ R ₂ ...(2) [However, Gm ₂ is the mutual conductance of the differential amplifier section consisting of the third and fourth transistors 10 and 11, R ₂ is the resistance value of the resistor 13, and C ₂ is the resistance value of the capacitor 14.
capacitance value]. Also, the mutual conductance of the differential amplifier section
Gm is, Gm=αqI/4KT×2=α/52I...(3) [However, T is the absolute temperature, q is the amount of charge of the electron,
K is the Boltzmann constant, α is the current amplification factor, and I is the current flowing through the constant current source of the differential amplifier section.] Therefore, the reactance circuit shown in FIG. 2 can be expressed as _{has a reactance X 1 of}
and X ₂ can be said to be a variable reactance circuit that can be changed by changing the currents of the variable current sources 4 and 12. In that case, in the above equations (1) and (2), Gm ₁ =Gm ₂ , C ₁ =C ₂ ,
By setting R ₁ = R ₂ and appropriately adjusting the current flowing through the variable current sources 4 and 12, the reactance circuit shown in FIG. 2 can obtain a reactance that linearly changes from a negative predetermined value to a positive predetermined value. I can do it. (c) Problems to be solved by the invention By the way, when implementing an integrated circuit, the transistors 16, 17 and diodes 18, 19 used in the current reversing circuits 7 and 15 in FIG. 2 are usually lateral PNP transistors. Consisted of. And the lateral PNP transistor has a cutoff frequency _T
is low, about 7MHz to 10MHz, so that the signal derived from the first transistor 2 in FIG. 2 to the input terminal 8 via the current inversion circuit 7 is
This depends on the frequency characteristics of the transistor, and as the frequency of the signal applied to the input terminal 8 increases, there is a risk that the circuit shown in FIG. 2 will not have correct reactance characteristics. In general, the frequency limit of the input signal is β cutoff frequency 〓 (= _T / β ₀ ; however,
β ₀ can be expressed as DC amplification factor), but horizontal
For PNP transistor, _T = 10MHz, β ₀ = 30
Then, 〓 = 333KHz, and a phase rotation of 45 degrees occurs at the frequency of 333KHz. And if the phase is rotated by 45 degrees, it becomes difficult to obtain the correct reactance. (d) Means for solving the problems The present invention has been developed in view of the above points, and includes first and second transistors whose emitters are commonly connected and which are the main components of the reactance circuit. The present invention is characterized in that the collector of the first transistor is connected to a power source, and the collector of the second transistor is connected to an input terminal together with the collector of a constant current transistor. (E) Effect According to the present invention, since the signal does not pass through the current inversion circuit composed of horizontal PNP transistors,
It is possible to provide a reactance circuit whose frequency characteristics are not limited and which maintains good reactance characteristics up to high frequencies. (F) Embodiment Figure 1 is a circuit diagram showing an embodiment of the present invention.
20 is a first reactance circuit that operates as a positive equivalent reactance when viewed from the input terminal 21 ;
A second reactance circuit 2 operates as a negative equivalent reactance when viewed from the input terminal 21. Therefore, the first reactance circuit 20
are first and second transistors 23 and 24 whose emitters are commonly connected; a first constant current transistor 25 whose collector is connected to the common emitters of the first and second transistors 23 and 24; a resistor 26 connected between the bases of the second transistors 23 and 24; a capacitor 27 connected between the base and collector of the second transistor 24;
4, and a bias circuit 29 that biases the first and second constant current transistors 25 and 28. Similarly, the second reactance circuit 22 includes third and fourth transistors 30 and 31, and third and fourth transistors 30 and 31.
Constant current transistors 32 and 33 and resistor 34
, a capacitor 35, and a bias circuit 36 that biases the third and fourth constant current transistors 32 and 33. Now, if the output current of the variable current source 37 is set to zero and the output current of the variable current source 38 is set to _I0 , the first reactance circuit 20 operates and the second reactance circuit 22 stops operating. In that case, the first
If the emitter area ratio of the fifth constant current transistors 25 and 39 is 2:1, the collector current of the first constant current transistor 25 is _I0 , and the collector current of the second and fifth constant current transistors is 2:1.
The collector currents of constant current transistors 28 and 39 become I ₀ /2. Further, the collector current I ₀ of the first constant current transistor 25 is divided into the first and second transistors 23 and 24, and the collector currents of the first and second transistors 23 and 24 when there is no signal are equal to I ₀ / It becomes 2. Therefore, when there is no signal, all the current supplied from the collector of the second constant current transistor 28 flows into the collector of the second transistor 24, and no current flows to the input terminal 21. Here, if an input signal of e ₀ is applied to the input terminal 21 and a current of i ₁ flows through the capacitor 27 in response, the current i ₁ is as follows: i ₁ = e ₀ /R+1/jωC...( 4) [However, R is the resistance value of the resistor 26, C is the capacitance of the capacitor 27, and ω is the angular frequency], and the first and second transistors 23 and 24
The base-to-base voltage e ₁ is as follows: e ₁ =i ₁ R=e ₀ R/R+1/jωC (5). On the other hand, the collector current i ₂ of the second transistor 24 is calculated from the equation (5) as i ₂ =Gme ₁ =e ₀ RGm/R+1/jωC (6) [However, Gm is 2
The mutual conductance _of the differential amplifier section consisting of 3 and ₂₄ is given by
From equations (4) and (6), i ₃ =i ₁ +i ₂ =e ₀ 1+RGm/R+1/jωC...(7). Applying the conditions for the first reactance circuit 20 to operate as a positive equivalent reactance (R≪1/jωC, 1≪RGm) to the above equation (7), we get the following:
The above equation (7) becomes i ₃ ≒e ₀ jωCRGm ...(7)', and the first reactance circuit 20
It is clear that this is the equivalent reactance of CRGm. Incidentally, as is clear from equation (3), the mutual conductance Gm is equal to the output current I ₀ of the variable current source 38.
Since the variable current source 38 is proportional to
By varying the output current I ₀ of , the circuit of FIG. 1 operates as a positive variable reactance circuit. Next, by setting the output current of the variable current source 38 to zero and the output current of the variable current source 37 to _I0 , the second reactance circuit 22 operates and the first reactance circuit 20 stops operating. In that case, if calculations similar to those shown above are performed, the reactance of the second reactance circuit 22 is -CRGm
(However, R is the resistance value of the resistor 34, C is the capacitance of the capacitor 35, and Gm is the mutual conductance.) It can be understood that the second reactance circuit 22 operates as a negative equivalent reactance. Then, by changing the output current _I0 of the variable current source 37 and changing the mutual conductance Gm, the circuit shown in FIG. 1 operates as a negative variable reactance circuit. In the embodiment of FIG. 1, the current flowing through the input terminal 21 is
This shows that i ₃ is set by the sum of the current i ₁ flowing through the capacitor 27 and the collector current i ₂ of the second transistor 24, and furthermore, the current i ₁ and i ₂
does not flow to the second constant current transistor 28 constituted by a lateral PNP transistor, so the current i ₃ flowing to the input terminal 21 is not subject to frequency limitation by the lateral PNP transistor. Therefore, the circuit shown in Figure 1 can fully enjoy the characteristics of an NPN transistor ( _T = 500MHz, β ₀ = 200, _B = 2.5MHz), and can provide a reactance circuit with excellent frequency characteristics. (g) Effects of the invention As described above, according to the invention, a reactance circuit that exhibits good reactance characteristics up to high frequencies can be obtained. Therefore, if the present invention is used for frequency control of a VCO (voltage controlled oscillator), it is possible to provide a VCO that can accurately control up to high frequencies.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional reactance circuit. Explanation of main drawing numbers, 20 ...First reactance circuit, 22 ...Second reactance circuit, 23...First transistor, 24...Second transistor, 2
5...first constant current transistor, 28...second constant current transistor.

Claims (1)

[Scope of utility model registration request] first and second transistors whose emitters are commonly connected; a first constant current transistor whose emitters are connected to a common emitter of the first and second transistors;
a resistor connected between the bases of the first and second transistors; a capacitor having one end connected to an input terminal and the other end connected to the resistor; and a second constant current transistor having a collector connected to the input terminal. A reactance circuit comprising: a collector of the first transistor connected to a power source; and a collector of the second transistor connected to the input terminal.