JPH0375557U - - Google Patents
Info
- Publication number
- JPH0375557U JPH0375557U JP13754389U JP13754389U JPH0375557U JP H0375557 U JPH0375557 U JP H0375557U JP 13754389 U JP13754389 U JP 13754389U JP 13754389 U JP13754389 U JP 13754389U JP H0375557 U JPH0375557 U JP H0375557U
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- substrate
- insulating substrate
- substrate via
- sectional area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 13
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
第1図aとbとcは本考案の一実施例を示す模
式的要部側断面図、第2図は本考案による基板ビ
アの特徴的性質を示す模式的要部側断面図、第3
図はaとbとcは従来の基板ビアの構造を示す模
式的要部側断面図、第4図は従来の基板ビアによ
つて発生する障害例を示す模式的要部側断面図で
ある。
図において、1……表面配線層、2……裏面配
線層、10,40……基板ビア、20……絶縁基
板、30,60……下孔、80……レーザ光線、
O……基板ビアの厚さ方向の中央ライン、α……
円錐状の傾斜面、d……基板ビア10の最小部分
(入り口部分)の断面積、D……基板ビア10の
最大部分(中央ラインOに対応する部分)の断面
積、△……クラツク、をそれぞれ示す。
Figures 1a, b, and c are schematic side sectional views of essential parts showing an embodiment of the present invention; Figure 2 is a schematic side sectional view of essential parts showing the characteristic properties of the substrate via according to the present invention;
In the figures, a, b, and c are schematic side sectional views of main parts showing the structure of conventional board vias, and FIG. 4 is a schematic side sectional view of main parts showing examples of failures caused by conventional board vias. . In the figure, 1... Surface wiring layer, 2... Back wiring layer, 10, 40... Substrate via, 20... Insulating substrate, 30, 60... Preparation hole, 80... Laser beam,
O... Center line in the thickness direction of the board via, α...
Conical inclined surface, d...Cross-sectional area of the smallest part (entrance part) of the substrate via 10, D...Cross-sectional area of the largest part (corresponding to the center line O) of the substrate via 10, Δ...Crack, are shown respectively.
Claims (1)
線層1と裏面配線層2を電気的に接続する基板ビ
アの構造において、 前記絶縁基板20を貫通する形で設けられる基
板ビア10を、前記表面配線層1と裏面配線層2
に接触する部分の断面積が最小で、前記絶縁基板
20の厚さ方向の中央ラインOに対応する部分の
断面積が最大となるように形成したことを特徴と
する基板ビアの構造。[Claims for Utility Model Registration] In the structure of a substrate via that electrically connects the front wiring layer 1 and the back wiring layer 2 formed on the front and back surfaces of the insulating substrate 20, the substrate via is provided to penetrate the insulating substrate 20. The substrate vias 10 are connected to the front wiring layer 1 and the back wiring layer 2.
A structure of a substrate via, characterized in that the cross-sectional area of a portion contacting the insulating substrate 20 is minimum, and the cross-sectional area of a portion corresponding to the center line O in the thickness direction of the insulating substrate 20 is maximum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13754389U JPH0375557U (en) | 1989-11-27 | 1989-11-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13754389U JPH0375557U (en) | 1989-11-27 | 1989-11-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0375557U true JPH0375557U (en) | 1991-07-29 |
Family
ID=31684695
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13754389U Pending JPH0375557U (en) | 1989-11-27 | 1989-11-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0375557U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007007861A1 (en) * | 2005-07-07 | 2007-01-18 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| KR100900671B1 (en) * | 2007-11-06 | 2009-06-01 | 삼성전기주식회사 | A method for forming conductive vias used in multilayer wiring boards |
| JP2010034258A (en) * | 2008-07-29 | 2010-02-12 | Kyocera Corp | Wiring substrate, mounting structure, and production process of wiring substrate |
-
1989
- 1989-11-27 JP JP13754389U patent/JPH0375557U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007007861A1 (en) * | 2005-07-07 | 2007-01-18 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| KR100900671B1 (en) * | 2007-11-06 | 2009-06-01 | 삼성전기주식회사 | A method for forming conductive vias used in multilayer wiring boards |
| JP2010034258A (en) * | 2008-07-29 | 2010-02-12 | Kyocera Corp | Wiring substrate, mounting structure, and production process of wiring substrate |