JPH03759Y2 - - Google Patents

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Publication number
JPH03759Y2
JPH03759Y2 JP15311583U JP15311583U JPH03759Y2 JP H03759 Y2 JPH03759 Y2 JP H03759Y2 JP 15311583 U JP15311583 U JP 15311583U JP 15311583 U JP15311583 U JP 15311583U JP H03759 Y2 JPH03759 Y2 JP H03759Y2
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JP
Japan
Prior art keywords
current
terminal
switch
differential
resistance element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP15311583U
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Japanese (ja)
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JPS6061842U (en
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Priority to JP15311583U priority Critical patent/JPS6061842U/en
Publication of JPS6061842U publication Critical patent/JPS6061842U/en
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Publication of JPH03759Y2 publication Critical patent/JPH03759Y2/ja
Granted legal-status Critical Current

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  • Electronic Switches (AREA)
  • Control Of Electrical Variables (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【考案の詳細な説明】 この考案は例えば複数の定電流源を設けて入力
デジタル信号に応じてその定電流源を選択出力し
て加算することによつてアナログ変換信号を得る
ようにしたデジタルアナログ変換器などに用いら
れる電流切替器に関する。
[Detailed description of the invention] This invention is based on a digital-to-analog system in which, for example, a plurality of constant current sources are provided, and an analog conversion signal is obtained by selectively outputting and adding the constant current sources according to an input digital signal. It relates to current switching devices used in converters and the like.

従来のこの種の電流切替器は第1図に示すよう
にFETQ1,Q2のソースが互に接続され、その接
続点は定電流源11を通じて負の電源端子12に
接続され、FETQ1,Q2のドレインは出力端子1
3,14とされる。この差動型FETスイツチ1
5を駆動するため差動型スイツチ駆動回路16が
設けられる。差動型スイツチ駆動回路16におい
てNPN形トランジスタQ3,Q4のエミツタは互に
接続されて定電流源17を通じて電源端子12に
接続され、各コレクタはそれぞれ抵抗器18,1
9を通じて電源端子21に接続される。トランジ
スタQ3,Q4の各ベースは入力端子22,23と
され、これら入力端子22,23間に切替信号が
印加される。スイツチ駆動回路16の出力端子は
トランジスタQ3のコレクタであつて、差動型
FETスイツチ15の一方の入力端子25、即ち
FETQ2のゲートに接続される。差動型FETスイ
ツチ15の他方の入力端子24は可変電源26に
接続される。
In the conventional current switching device of this kind, as shown in FIG . The drain of Q 2 is output terminal 1
3.14. This differential FET switch 1
A differential switch drive circuit 16 is provided to drive the switch 5. In the differential switch drive circuit 16, the emitters of NPN transistors Q 3 and Q 4 are connected together and connected to the power supply terminal 12 through a constant current source 17, and the collectors of each are connected to resistors 18 and 1, respectively.
It is connected to the power supply terminal 21 through 9. The bases of the transistors Q 3 and Q 4 serve as input terminals 22 and 23, and a switching signal is applied between these input terminals 22 and 23. The output terminal of the switch drive circuit 16 is the collector of the transistor Q3 , which is a differential type
One input terminal 25 of the FET switch 15, i.e.
Connected to the gate of FETQ 2 . The other input terminal 24 of the differential FET switch 15 is connected to a variable power supply 26.

入力端子22が負側、端子23が正側となるよ
うにスイツチ制御信号を印加すると、トランジス
タQ3がオフとなりトランジスタQ4がオンとなつ
て入力端子25が入力端子24よりも高レベルと
なつてFETQ2が導通し、FETQ1がオフとなる。
逆に入力端子22を正側、入力端子23を負側と
なる制御信号が印加されると、トランジスタQ3
がオンとなつてFETQ2のゲートが入力端子24
よりも低レベルとなつてFETQ2がオフとなつて
FETQ1がオンとなる。このようにして出力端子
13に対し、定電流源11の定電流を切替え供給
することができる。
When a switch control signal is applied so that input terminal 22 is on the negative side and terminal 23 is on the positive side, transistor Q 3 is turned off, transistor Q 4 is turned on, and input terminal 25 becomes at a higher level than input terminal 24. FETQ 2 becomes conductive and FETQ 1 turns off.
Conversely, when a control signal is applied that sets input terminal 22 on the positive side and input terminal 23 on the negative side, transistor Q 3
is turned on and the gate of FETQ 2 is connected to input terminal 24.
FETQ 2 turns off as the level becomes lower than
FETQ 1 turns on. In this way, the constant current of the constant current source 11 can be switched and supplied to the output terminal 13.

このような動作を正しく行わせるため、次のよ
うに調整される。まずトランジスタQ3をオフと
して端子25に端子21の電源電圧を与えて
FETQ2をオンとし、その状態で電源26の電圧
を調整して端子24に与える電位を徐々に下げ、
これをFETQ1がオフとなるまで行う。その後ト
ランジスタQ3をオンとし、更に定電流源17の
電流を徐々に増加してFETQ2がオフとなるまで
電流源17の電流を増加する。このようにして入
力端子24に印加する電圧に対して入力端子25
の電圧がΔVだけ高レベルでFETQ2がオンとな
り、入力端子24に対して入力端子25がΔVだ
け低い場合にFETQ1がオンとなる。
In order to perform this operation correctly, the following adjustments are made. First, turn off transistor Q3 and apply the power supply voltage of terminal 21 to terminal 25.
Turn on FETQ 2 , adjust the voltage of power supply 26 in that state, gradually lower the potential applied to terminal 24,
Do this until FETQ 1 turns off. Thereafter, transistor Q 3 is turned on, and the current of constant current source 17 is gradually increased until FET Q 2 is turned off. In this way, the voltage applied to the input terminal 24 is
FETQ 2 is turned on when the voltage of ΔV is high, and when input terminal 25 is lower than input terminal 24 by ΔV, FETQ 1 is turned on.

このように第1図に示した電流切替器において
は最低2回の調整を必要するが、実際には最初に
電源26の電圧の設定時においても1回で必ずし
も良好な値にはならず、繰返し調整をする必要が
あり、従つて先に述べたDA変換器のように多数
の電流源を設けてその出力をオン、オフするため
の電流切替器として使用するにはそのすべての電
流切替器の調整に多くの手数を必要とする欠点が
ある。
In this way, the current switch shown in FIG. 1 requires adjustment at least twice, but in reality, even when setting the voltage of the power supply 26 for the first time, it is not always possible to obtain a good value with just one adjustment. It is necessary to make repeated adjustments, so in order to use a current switch to turn on and off the output of multiple current sources like the DA converter mentioned above, all of the current switches must be used. The disadvantage is that it requires a lot of effort to adjust.

一方従来において第2図に第1図と対応する部
分に同一符号を付けて示すように、スイツチ駆動
回路16のトランジスタQ3,Q4の各コレクタを
差動型FETスイツチ15の入力端子25,24
にそれぞれ接続したものもある。この場合におい
てはスイツチ駆動回路のトランジスタQ3,Q4
一方のコレクタが高レベルの時、他方のコレクタ
は低レベルとなつているため、スイツチ駆動回路
のトランジスタQ3,Q4のオンオフ状態を切替え
ることによつてFETQ1,Q2のオンオフ状態を切
替えることができる。
On the other hand , in the prior art, as shown in FIG. 2 with the same reference numerals assigned to parts corresponding to those in FIG. 24
Some are connected to each other. In this case, when one collector of transistors Q 3 and Q 4 in the switch drive circuit is at a high level, the other collector is at a low level, so the on/off state of transistors Q 3 and Q 4 in the switch drive circuit is By switching, the on/off states of FETQ 1 and Q 2 can be switched.

この場合におけるスイツチ動作の調整は、例え
ばトランジスタQ3をオン、トランジスタQ4をオ
フの状態として電流源17の電流をゼロとし、
FETQ1,Q2は共にオンの状態とし、この状態よ
り電流源17の電流を増加し、これに伴つて
FETQ2の電位が下つてきてFETQ2がオフとなる
まで電流を増加する。この回路は1回の調整で済
む特徴がある。しかし出力端子13側に接続され
ているFETQ1のゲート、つまり入力端子24は
FETスイツチ15の切替動作ごとにゲート電位
が変化し、これがスパイク状に雑音として出力端
子13に現われ、出力波形の品質を劣化させる欠
点があつた。
Adjustment of the switch operation in this case involves, for example, turning on the transistor Q 3 and turning off the transistor Q 4 to set the current of the current source 17 to zero.
FETQ 1 and Q 2 are both in the on state, and from this state the current of the current source 17 is increased, and along with this,
Increase the current until the potential of FETQ 2 drops and FETQ 2 turns off. This circuit has the characteristic that only one adjustment is required. However, the gate of FETQ 1 connected to the output terminal 13 side, that is, the input terminal 24
The gate potential changes every time the FET switch 15 switches, and this appears as spike-like noise at the output terminal 13, which has the disadvantage of deteriorating the quality of the output waveform.

この考案はこのような点より調整が簡単でしか
も出力側のFETのゲートは一定電圧が印加され、
出力にスパイク雑音が混入することがない電流切
替器を提供するものである。
This idea is easier to adjust than above, and a constant voltage is applied to the gate of the FET on the output side.
The present invention provides a current switch that does not cause spike noise to be mixed into the output.

次にこの考案による電流切替器の実施例を第3
図を参照して説明する。第3図において第1図及
び第2図と対応する部分には同一符号を付けてあ
る。この実施例においては差動型FETスイツチ
15の入力端子24,25はそれぞれ抵抗素子2
8,29を通じて電源端子21に接続される。ま
た可変電流分配回路31が設けられる。即ち可変
電流分配回路31はNPN形トランジスタQ5,Q6
を備え、これらトランジスタQ5,Q6の各エミツ
タは可変電流源17を通じて電源端子12に接続
され、この例においては各ベースは互に接続され
て電源端子32に接続されている。トランジスタ
Q5,Q6にそれぞれ電流源17の電流の1/2の
電流が出力される。この分配比を保持した状態で
出力電流を増減することができるようにされる。
分配電流の一方、即ちトランジスタQ5のコレク
タ電流は抵抗素子28に供給される。そのためこ
のトランジスタQ5のコレクタはFETスイツチ1
5の入力端子24に接続される。分配電流の他
方、即ちトランジスタQ6のコレクタ電流は差動
型スイツチ駆動回路16の切替電流として供給さ
れ、即ちトランジスタQ6のコレクタはトランジ
スタQ3,Q4のエミツタに接続される。抵抗素子
28の抵抗値をR1、抵抗素子29の抵抗値をR2
とし、かつ R1=1/2R2 に選定されている。
Next, a third example of the current switching device according to this invention will be described.
This will be explained with reference to the figures. In FIG. 3, parts corresponding to those in FIGS. 1 and 2 are given the same reference numerals. In this embodiment, the input terminals 24 and 25 of the differential FET switch 15 are connected to the resistor elements 2 and 25, respectively.
It is connected to the power supply terminal 21 through 8 and 29. A variable current distribution circuit 31 is also provided. That is, the variable current distribution circuit 31 is composed of NPN transistors Q 5 and Q 6
The emitters of these transistors Q 5 and Q 6 are connected to the power supply terminal 12 through a variable current source 17, and in this example, their bases are connected to each other and connected to the power supply terminal 32. transistor
A current that is 1/2 of the current of the current source 17 is output to Q 5 and Q 6 , respectively. The output current can be increased or decreased while maintaining this distribution ratio.
One of the distributed currents, ie, the collector current of transistor Q 5 , is supplied to resistive element 28 . Therefore, the collector of this transistor Q5 is FET switch 1
It is connected to the input terminal 24 of No. 5. The other of the distributed currents, that is, the collector current of transistor Q6 , is supplied as a switching current to the differential switch drive circuit 16, that is, the collector of transistor Q6 is connected to the emitters of transistors Q3 and Q4 . The resistance value of the resistance element 28 is R 1 , and the resistance value of the resistance element 29 is R 2
and R 1 = 1/2R 2 .

この構成において、この電流切替器を調整する
にはFETQ2をオフ、Q1をオンとし、つまりトラ
ンジスタQ3をオンとし、この状態で電流源17
の電流Iをゼロから増加する。即ち当初において
はFETQ1,Q2の入力端子24,25は電源端子
21の電圧が与えられ、共にオン状態であるが、
電流Iを増加するに従つて抵抗素子28における
電圧降下よりも抵抗素子29における電圧降下
が、先に述べた抵抗値のために2倍であるため、
最初端子24の電圧と端子25の電圧が等しい
が、電流Iの増加に従つて端子25の電圧が端子
24の電圧よりも下り、その差が大きくなつてき
て遂に、FETQ2がオフ、FETQ1がオンとなる。
この状態で調整が終了するが、この時端子25に
対し端子24はΔVだけ高い。
In this configuration, to adjust this current switch, turn off FET Q 2 and turn on FET Q 1 , that is, turn on transistor Q 3 , and in this state, current source 17
Increase the current I from zero. That is, initially, the input terminals 24 and 25 of FETQ 1 and Q 2 are supplied with the voltage of the power supply terminal 21, and are both in the on state.
As the current I is increased, the voltage drop across the resistive element 29 is twice as high as the voltage drop across the resistive element 28 due to the previously mentioned resistance value;
Initially, the voltage at terminal 24 and the voltage at terminal 25 are equal, but as the current I increases, the voltage at terminal 25 drops below the voltage at terminal 24, and as the difference becomes larger, FETQ 2 is turned off and FETQ 1 is turned off. turns on.
The adjustment is completed in this state, but at this time, the terminal 24 is higher than the terminal 25 by ΔV.

この時端子24の電圧は I/2R1 端子25の電圧は 1/2IR2=I/2×2R1 となり、これら端子24及び25の電圧比 Vg1/Vg2=1/2 となり、この時スイツチ駆動回路16を反転して
トランジスタQ3をオフ、トランジスタQ4をオン
とすると端子25側が端子24に対して先のΔV
だけ大となつてFETQ2がオン、FETQ1がオフと
なる。
At this time, the voltage at terminal 24 is I/2R, and the voltage at terminal 25 is 1/2IR 2 = I/2×2R 1 , and the voltage ratio of these terminals 24 and 25 is V g1 /V g2 = 1/2. At this time, When the switch drive circuit 16 is reversed and transistor Q 3 is turned off and transistor Q 4 is turned on, the terminal 25 side becomes the first ΔV with respect to the terminal 24.
becomes large, FETQ 2 turns on and FETQ 1 turns off.

電流切替スイツチ15に対して要求される特性
は第4図に示すように入力電圧Vi、つまり端子2
4と25との電位差Vg1−Vg2が入力端子24の
電圧Vg1を中心にして電流源11の電流が小さい
場合は曲線34,35に示すようにVg1に対して
対称となり、また電流源11の電流が大きい場合
は曲線36,37に示すようにやはり同一とな
り、しかも対称となつてその立上り、出力電流I0
がそれぞれ定電流Isに達するまでの必要な入力、
つまり端子24に対する端子25の電圧変化の最
低値が電流Isが大きい程大きくなる。
The characteristics required for the current selector switch 15 are as shown in FIG .
When the current of the current source 11 is small , the potential difference V g1 -V g2 between 4 and 25 is symmetrical to V g1 as shown in curves 34 and 35, and the current When the current of the source 11 is large, as shown in curves 36 and 37, they are the same and symmetrical, and their rise and output current I 0
The required input until each reaches a constant current I s ,
In other words, the minimum value of the voltage change at the terminal 25 with respect to the terminal 24 increases as the current I s increases.

このような関係が先に述べたようにFETQ2
オフとした状態で電流源17の電流Iを0より増
加することによつて1度の調整によつて得られ
る。しかも電流の切替動作においては端子24の
電圧Vg1は一定値が与えられており、従つて出力
端子13に電流切替動作に基づくスパイク雑音は
現れない。
As described above, such a relationship can be obtained by one adjustment by increasing the current I of the current source 17 from 0 with FETQ 2 turned off. Furthermore, during the current switching operation, the voltage V g1 at the terminal 24 is given a constant value, so that no spike noise occurs at the output terminal 13 due to the current switching operation.

可変電流分配回路31として可変電流源17を
省略してその替りに第5図に示すように可変抵抗
器38を接続してその抵抗値を変化させてもよ
い。また第3図、第5図の構成において例えば第
6図に示すように電流分配回路31においてトラ
ンジスタQ5,Q6のエミツタ間に可変抵抗器39
の両端を接続し、可変抵抗器39の可動子を可変
電流源17に接続して可変抵抗器39を調整して
トランジスタQ5,Q6に流れる電流を等しく制御
することもできる。また上述においては抵抗素子
28に対して抵抗素子29の抵抗値を2倍とした
が、抵抗素子28,29の抵抗値を同一値とし、
抵抗素子29に流れる電流を抵抗素子28に流れ
る電流の2倍となるように電流分配回路31を構
成してもよい。要するに抵抗素子28に発生する
電圧降下の変化よりも、抵抗素子29に発生する
電圧降下が大きくなるようにすればよい。差動型
FETスイツチ15の代りに差動型トランジスタ
スイツチを用いてもよい。つまりFETQ1,Q2
代りにバイポーラトランジスタを用いて構成して
もよい。
The variable current source 17 may be omitted from the variable current distribution circuit 31, and instead, as shown in FIG. 5, a variable resistor 38 may be connected to change its resistance value. In addition, in the configurations of FIGS. 3 and 5, for example, as shown in FIG. 6, a variable resistor 39 is connected between the emitters of transistors Q 5 and Q 6 in the current distribution circuit 31.
It is also possible to connect both ends of the variable resistor 39 and connect the mover of the variable resistor 39 to the variable current source 17 to adjust the variable resistor 39 to equally control the currents flowing through the transistors Q 5 and Q 6 . Furthermore, in the above description, the resistance value of the resistance element 29 is twice that of the resistance element 28, but the resistance values of the resistance elements 28 and 29 are assumed to be the same value,
The current distribution circuit 31 may be configured so that the current flowing through the resistive element 29 is twice the current flowing through the resistive element 28. In short, it is only necessary to make the voltage drop occurring in the resistance element 29 larger than the change in the voltage drop occurring in the resistance element 28. differential type
A differential transistor switch may be used instead of the FET switch 15. In other words, bipolar transistors may be used instead of FETQ 1 and Q 2 .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は従来の電流切替器を示す接
続図、第3図はこの考案による電流切替器の一例
を示す接続図、第4図は第3図における電流切替
器の入力に対する出力電流特性図、第5図は可変
電流分配回路の他の例を示す接続図、第6図はこ
の考案による電流切替器の他の例を示す接続図で
ある。 11:定電流源、12:電源端子、13:出力
端子、15:差動型FETスイツチ、16:スイ
ツチ駆動回路、17:可変電流源、31:可変電
流分配回路。
Figures 1 and 2 are connection diagrams showing a conventional current switch, Figure 3 is a connection diagram showing an example of the current switch according to this invention, and Figure 4 is the output for the input of the current switch in Figure 3. A current characteristic diagram, FIG. 5 is a connection diagram showing another example of the variable current distribution circuit, and FIG. 6 is a connection diagram showing another example of the current switching device according to this invention. 11: constant current source, 12: power supply terminal, 13: output terminal, 15: differential FET switch, 16: switch drive circuit, 17: variable current source, 31: variable current distribution circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 差動型半導体スイツチと、その差動型半導体ス
イツチの共通接続端に接続された定電流源と、ス
イツチ制御信号により切替制御され、一方の出力
端が上記差動型半導体スイツチの第1入力端に接
続された差動型スイツチ駆動回路とを具備した電
流切替器において、上記差動型半導体スイツチの
第1、第2入力端と電源端子との間にそれぞれ接
続された第1、第2抵抗素子と、分配比を保持し
て出力電流を変化することができる電流分配回路
とを備え、その電流分配回路の一方の分配電流は
上記スイツチ駆動回路に切替電流として供給さ
れ、上記電流分配回路の他方の分配電流は上記第
2抵抗素子に供給され、上記電流分配回路の電流
の変化により、上記第1抵抗素子及び第2抵抗素
子における降下電圧の変化が第1抵抗素子の方が
大となるように選定されている電流切替器。
Switching is controlled by a differential semiconductor switch, a constant current source connected to a common connection terminal of the differential semiconductor switch, and a switch control signal, and one output terminal is connected to the first input terminal of the differential semiconductor switch. In the current switching device, the current switching device includes a differential type switch drive circuit connected to the differential type semiconductor switch, and first and second resistors respectively connected between the first and second input terminals of the differential type semiconductor switch and the power supply terminal. and a current distribution circuit that can change the output current while maintaining the distribution ratio, one distribution current of the current distribution circuit is supplied to the switch drive circuit as a switching current, and the current distribution circuit of the current distribution circuit is supplied as a switching current to the switch drive circuit. The other distributed current is supplied to the second resistance element, and due to a change in the current in the current distribution circuit, the change in voltage drop across the first resistance element and the second resistance element is greater in the first resistance element. The current switching device is selected as follows.
JP15311583U 1983-09-30 1983-09-30 current switcher Granted JPS6061842U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15311583U JPS6061842U (en) 1983-09-30 1983-09-30 current switcher

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15311583U JPS6061842U (en) 1983-09-30 1983-09-30 current switcher

Publications (2)

Publication Number Publication Date
JPS6061842U JPS6061842U (en) 1985-04-30
JPH03759Y2 true JPH03759Y2 (en) 1991-01-11

Family

ID=30338847

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15311583U Granted JPS6061842U (en) 1983-09-30 1983-09-30 current switcher

Country Status (1)

Country Link
JP (1) JPS6061842U (en)

Also Published As

Publication number Publication date
JPS6061842U (en) 1985-04-30

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