JPH0376100A - Method and device for sampling of high speed digital signal - Google Patents

Abstract

PURPOSE:To easily execute sampling of a high speed digital signal by a clock of a low speed by executing the sampling by shifting the phase of the signal by using a flip-flop and a delay element. CONSTITUTION:A high speed digital signal S1 and a clock CLK are inputted to a first flip-flop FF1, and by synchronizing with the rise of a clock CLK, a signal A of an H level is outputted. The high speed digital signal S1 is inputted successively to a first, a second,... delay elements RE1, RE2,... and delayed, outputs of each delay element RE1, RE2,... and the clock CLK are inputted to a second, a third,... flip-flops FF2, FF3,..., and signals B, C,... of an H level synchronizing with a rise of the clock CLK are outputted. To a discriminating part JP, signals A, B,... are inputted, and by their decision of majority, a signal Sh of an H level is inputted. In such a way, sampling of the high speed digital signal S1 can be executed even by the sampling clock CLK of a low speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method and apparatus in the field of high-speed transmission such as high-speed deleveling, in which sampling of high-speed deleveling can be performed even with a low-speed clock.

[Conventional technology and its issues]

Conventionally, as shown in Figure 3, high-speed delevel S1 and clock C
LK is input to flip-flop FF, and from this signal S is synchronized with clock CLK. Since this is a method and device for outputting
As shown in the figure, for the input signal (high-speed delevel) SI of the flip-flop FF, a signal S0 synchronized with the rising edge of the clock CLK, which is faster than the flip-flop FF, is obtained, and the high-speed delevel SI can be sampled.
When LK is low speed, as shown in FIG. 4(b), the input signal SI of flip-flop FF is
A signal S synchronized with the rising edge of clock CIJ, which is slower than F.
0 is obtained, and as can be seen from the comparison with the case where a high-speed clock shown in FIG. 4(a) is used, sampling of the high-speed digital nanoray word SI cannot be performed using a low-speed clock.

In order to be able to sample the high-speed delevel SI, the clock CLK must be at least twice as fast as the high-speed delevel S, and the peripheral circuit elements must also operate quickly. There was a problem.

[Means to solve the problem]

In order to solve the above problems, the method of the present invention uses a flip-flop and a delay element for high-speed delevel sampling to shift the phase of the signal and performs sampling with the same clock. It is characterized by enabling delevel sampling.

In order to solve the same problem, the device of the present invention has a 17th circuit which inputs high-speed delevel S+ and clock CLK as shown in the first diagram.
a required number of first, second...delay elements RE that sequentially delay and output the lip-flop FP and the high-speed delevel S;
, RE,... and the first and second delay elements RE, , R
The second .E, which inputs the outputs of . Third…
Flip-flops FF, FF, . . . and the first .
Output A of second...flip-flop FF, , FF,...
, B, . . . and outputs A, B, .

This configuration includes a determination section JP that outputs a signal sh at H level.

[For production]

The high-speed delevel s1 and the clock CLK are input to the first flip-flop FF, which outputs an H-level signal A in synchronization with the rise of the clock CLK. The high-speed delevel S1 is the first one. Second...delay element REI, REg...
The output of each delay element RE, , RE, ... and the clock CL are sequentially input and delayed.
K is the second. 3rd... flip-flops FF, FFs..., and these second... flip-flops FF, FFs... 3rd...Flip-flop FF
H-level signals B, C, etc. synchronized with the rising edge of the clock CIJ are outputted from the FFs, z, FFs, and so on. Discrimination part JP
These signals A, B, C, . . . are input to the circuit, and an H level signal sh is outputted by a majority vote of these signals A, B, C, .

At this point, an H level signal sh is output.

〔Example〕

The present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing the structure of an embodiment of the method and apparatus of the present invention, where S is a high-speed delevel and CLK is a low-speed clock in this embodiment. F.P.

is this high-speed delevel SI and low-speed clock CLK (second
(see figure) and outputs a signal A (see figure 2) synchronized with the rising edge of clock CLK. This is a second delay element.

Δt is the time delayed by the first delay element RE+, Δ
t2 is the time delayed by the second delay element REz (second
(see figure).

ppz inputs the high-speed delevel delayed by Δt1 time and the clock CLK by the first delay element RE, and outputs the clock CLK.
The second flip-flop, FFs, outputs the signal B (see FIG. 2) synchronized with the rising edge of LK. The second delay element RIE+, REI causes Δ1. This is the third flip-flop which inputs the high-speed delevel delayed by +Δt2 time and the clock CLK, and outputs the signal C (see FIG. 2) synchronized with the rising edge of the clock CLK.

The determining unit JP receives these signals A, B, and C, and outputs an H-level signal sh based on a majority vote of the signals A, B, and C. The operation table of this determination unit JP is shown below.

As is clear from this operation table, inputs A and B of determination unit JP
, C, the output sh is determined by majority vote. For example, when inputs A, B, and C are at 0.1.1 level, the output is at 1 level (
Similarly, when the level is 1°0.1, the level is 1, when the level is 1,1.0, the level is 1, and when the level is 1,1.1, the level is 1.

At the bottom of the tank, the high-speed delevel SI and the low-speed clock CLK (see Figure 2) are connected to the first flip-flop FP.
, and an H-level signal A synchronized with the rising edge of the clock CLK, which is slower than this, is output. The high-speed delevel S is inputted to the first delay element RBI and delayed by Δt3 time, and further inputted to the second delay element RH2 and delayed by Δt2 time.

The output of the first delay element RE (Δ1. time-delayed high-speed deleveling, see Figure 2) and the low-speed clock CLK are connected to the second delay element RE.
An H level signal B (see FIG. 2) which is input to the flip-flop FFz and synchronized with the rise of the clock CLK, which is slower than the flip-flop FFz, is output.

In addition, the output of the second delay element RE (high-speed delevel delayed by Δtl + Δt8 hours, see Figure 2) and the low-speed clock CLK are input to the third flipflop FF3, and synchronized with the rise of the slower clock CLK. An H level signal C (see FIG. 2) is output.

The outputs A, B, and C of the first to third flip-flops FF, to PF3 are input to the determination unit JP, and these signals A,
Based on the majority decision between B and C, an H level signal sh is output. (See Figure 2).

Thus, the high-speed delevel S shown in the second diagram can easily perform sampling using a low-speed clock without changing the high-speed clock or the peripheral circuit elements to fast-operating elements as in the conventional case.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the method and apparatus shift the phase of the signal using flip-flops and delay elements for high-speed delevel sampling, and sample with the same clock. High-speed delevel sampling can be easily performed using a low-speed clock without using fast-acting devices or peripheral circuit elements.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the tank bottom of an embodiment of the method and apparatus of the present invention, FIG. 2 is a timing chart for explaining the operation of the present invention, and FIG. 3 is a diagram showing the configuration of an example of the conventional method and apparatus. FIGS. 4(a) and 4(b) are timing charts for explaining the operation when conventional high-speed and low-speed clocks are used, respectively. SL...High-speed delevel, CLK...Clock, RE,
, REt... is the first. 2nd...delay element, FF, FF2
... is the first. The second... flip-flops, A, B... are the first...
Output signal of second...flip-flop FF, FFz..., J
P...determination section, sh...H level signal. Output signals of FF, FFz..., JP...
. . . Judgment unit, sh . . . H level signal.

Claims (2)

[Claims] (1) By using a method of sampling high-speed digital signals by shifting the phase of the signals using flip-flops and delay elements and sampling with the same clock, it is possible to sample high-speed digital signals even with a low-speed sampling lock. A high-speed digital signal sampling method characterized by: (2) A first flip-flop FF_1 that inputs the high-speed digital signal s_1 and the clock CLK, and a required number of first and second flip-flops that sequentially delay and output the high-speed digital signal S_1.
...Delay elements RE_1, RE_2... and the first, second...
Outputs of delay elements RE_1, RE_2... and clock CL
Second and third flip-flops FF_2 that input K
FF_3... and the outputs A, B... of the first and second flip-flops FF_1, FF_2... are input, and an H level signal Sh is output by majority vote based on the input of those outputs A, B... A high-speed digital signal sampling device comprising a determining unit JP.