JPH0376477A - Noise removal circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a noise removal circuit for extracting image signals from a solid-state imaging device.

BACKGROUND OF THE INVENTION In recent years, noise removal circuits for extracting the above-mentioned image signals are generally CD5 (Collerated Double
It is widely used as a sampling (correlated double sampling) method. A conventional noise removal circuit will be explained below.

Figure 2 is from the IEEE Journal of Solid State Circuits, published in February 1974.
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5c-9. This is a sample-and-hold circuit that operates by pulses. Note that 6 is an inverting amplifier, 5 is a signal input terminal, and 7 is an output terminal. The operation of the noise removal circuit configured as above will be explained below. First, an output signal from the solid-state imaging device is input to the clamp circuit 1 from the signal input terminal 5, and is clamped to an arbitrary voltage according to the timing of a clamp pulse input from the pulse input terminal 3. Next, when input to the sample hold circuit 2, an image signal is extracted according to the timing of the sampling pulse input from the pulse input terminal 4, and is outputted from the output terminal 7 via the inverting amplifier 6. As a result, reset noise generated in the output capacitance of the solid-state imaging device is removed, and furthermore, it is possible to reduce random noise generated in the CCD output signal.

Problems to be Solved by the Invention However, in the conventional configuration described above, the clock frequency component of the sampling pulse is multiplied by the output component by the sampling circuit, and an LO filter such as a low-pass filter is required at the output terminal 7 of the conventional example. There was a drawback that. The present invention solves the above-mentioned conventional problems, and aims to provide a noise removal circuit having sampling pulse leakage and an inverting amplifier.

Means for Solving the Problems To achieve this object, the noise removal circuit of the present invention includes a reference voltage source, a clamp circuit that clamps a signal from an imaging device, and a sample output signal of the clamp circuit using a sampling pulse. A first sampling circuit that holds the output voltage of the reference voltage source used for clamping, and a second sampling circuit that samples and holds the output voltage of the reference voltage source used for clamping using the sampling pulse; and a subtraction processing amplifier for subtracting the output signal from the first sampling circuit for extraction.

Effect: With this configuration, the output signal of the sampling means for sampling the output voltage of the reference voltage source and the extraction signal are subjected to subtraction processing, so that the clock frequency component of the sampling pulse can be removed.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration diagram of a noise removal circuit in an embodiment of the present invention. In FIG. 1, 21 is a clamp circuit, 22 is a first sample and hold circuit, 23
is a second sample and hold circuit, 24 is a reference voltage source, 2
5 is a subtraction processing amplifier.

The operation of the noise removal circuit of this embodiment configured as described above will be explained below. First, signal input terminal 26
The reference voltage source 24 is input in the clamp circuit 21 by the clamp pulse indicating the clamp timing input from the pulse input terminal 27.
Clamp to the output voltage value output at Next, this signal is input to the first sample and hold circuit 22, and sampled and held using a sampling pulse indicating the sampling timing inputted from the pulse input terminal 28.

At the same time, the second sample and hold circuit 23 samples and holds the output voltage of the reference voltage source 24 using a sampling pulse from the pulse input terminal 28 similar to that of the first sample and hold circuit 22. The first sample-hold output signal and the second sample-hold output signal are input to a subtraction processing amplifier 25 in which the former is negative and the latter is positive, and the signal from which the clock frequency component of the sampling pulse has been removed is converted into a positive polarity signal. Output with .

As described above, according to this embodiment, the clock frequency component generated in the sample and hold circuit can be removed by the in-phase removal effect of the subtraction circuit.

Effects of the Invention The present invention realizes an excellent noise removal circuit that can remove sampling clock frequency components by providing a second sample and hold circuit separate from the first sample and hold circuit for signal extraction. It is.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a noise removal circuit according to an embodiment of the present invention, and FIG. 2 is a configuration diagram of a conventional noise removal circuit. 1... Clamp circuit, 2... Sample hold circuit, 3... Pulse input terminal for clamping, 4... Pulse input terminal for sampling, 5
...Input terminal for solid-state imaging device output signal, 6...
...Inverting amplifier, 7...Output terminal, 21.
... Clamp circuit, 22 ... First sample and hold circuit, 23 ... Second sample and hold circuit, 24 ... Reference voltage source, 25 ...・
... Subtraction processing amplifier, 26 ... Input terminal for image sensor output signal, 27 ... Pulse input terminal for clamping, 28 ... Pulse input terminal for sample hold, 29 ...Output terminal.

Claims (1)

[Claims] a reference voltage source; a clamp circuit that clamps an output signal from the imaging device to an output voltage value output from the reference voltage source using a clamp pulse indicating clamp timing;
a first sample and hold circuit that samples and holds an output signal from the clamp circuit using a sampling pulse indicating sampling timing; a second sample and hold circuit that samples and holds an output voltage of the reference voltage source using the sampling pulse; The present invention is characterized by comprising a subtraction processing amplifier that performs subtraction processing on the output signal of the first sample and hold circuit and the output signal of the second sample and hold circuit, and outputs a signal obtained by removing the clock frequency component of the sampling pulse. Noise removal circuit.