JPH0377178A - Image processor - Google Patents

Abstract

PURPOSE:To extend the image memories, the data processing circuits, etc., and also to attain a flexible pipeline process using these extended memories and circuits by scattering the bus connection control circuits on an image ring bus so as to avoid the conflict of buses. CONSTITUTION:An image input input circuit 2 is provided together with the image memories 31 and 32, the data processing circuits 41 and 42, an image output circuits 51, and the bus connection control circuits 101 - 106 which are scattered on an image bus and attain the optional connection to the image bus. The image buses connecting those control circuits are defined as the ring buses 75 - 77. Thus the connection can be changed and an optional pipeline process is attained. Then the buses 75 - 77 can vary flexibly their connection states under the control of a CPU. As a result, the conflict of the ring buses is avoided and an optional pipeline process is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that processes digital image information captured by a television camera and converted into a multi-valued image.

(Conventional technology) Conventionally, in order to perform pattern recognition on a grayscale image, the entire image is first subjected to preprocessing such as density conversion and differentiation, and the feature points that make up the edges in the image are extracted, and then the feature points that make up the edges in the image are extracted. After creating a line drawing, the features of the line drawing are extracted and patterns are recognized. This kind of processing can be done by CPU
When executed using software processing, the disadvantage is that the processing time is slow due to the huge amount of image data. Therefore, although the processing content is simple, many image processing apparatuses use a dedicated data processing circuit for the preprocessing section, which involves a large amount of data and takes the most time, to speed up the process.

FIG. 5 shows a configuration diagram of a conventional image processing device as shown, for example, in Toshiba Review Vol.
(3) is an image memory that stores image data; (4) is a dedicated data processing circuit that performs preprocessing at high speed; (5) is an image output circuit that displays image data on a monitor (6); 71) to (74) are four systems of image buses for transmitting image data, and (8) is a CPU that controls the operation of the apparatus via a system bus (9).

Next, the operation will be explained. An image signal captured by a television camera (1) is input to an image input circuit (2), multivalued for each pixel, and stored in an image memory (3) via an image bus (71). A signal obtained by sequentially reading out the stored image data or an output signal of the image input circuit (2) is sent to the data processing circuit (71) sequentially via the image bus (71).
4), pre-processing such as density conversion and differentiation is executed at high speed, and the processing results are sequentially stored in the image memory (3) via the image bus (72). This stored image data of the processing result is processed by cpo (a) in a timely manner via the system bus (9) controlled by CP[J (a),
Feature extraction is performed. In addition, the processing results are stored in the image memory (
3), or from the data processing circuit (4) to the image bus (7).
Image output circuit (5) via any one of 1) to (74)
or from the CPU (8) to the system bus (9)
is sent to the image output circuit (5) via the monitor (6).
will be displayed.

The image processing device shown in FIG.
1) to (74) are provided, and the data processing circuit (4) receives sequentially sent image data while outputting the processing results, thereby increasing the speed of preprocessing.

Furthermore, by increasing the types of data processing circuits, processing capacity can be increased.

(Problems to be Solved by the Invention) Conventional image processing devices are composed of a data processing circuit and four image buses as described above, so no matter how much the data processing circuit is strengthened, the image bus cannot be used. There was a problem that arbitrary pipeline processing could not be performed due to contention.

FIG. 6 is an explanatory diagram of the vibration line processing, and it is assumed that processings A to E are performed in data processing circuits (41) to (45), respectively. Vibration processing is a method that performs continuous processing by passing the processing results of the previous stage as human power in the next stage, reducing the overall processing time, but in Figure 6 (a), only three stages of Vibration processing are performed. Can not. That is, the image bus (7
The image data inputted through the data processing circuit (4)
In step 1), process A is executed, and the sequentially outputted process results are manually input to the data processing circuit (42) via the image bus (72), and process B is executed. The processing results sequentially output from processing B are manually input to the data processing circuit (43) via the image bus (73), and processing C is executed. The output of processing C is transferred to the image bus (74
), and data flows simultaneously to all four image buses (solid arrows in FIG. 6(a)). Therefore, due to image bus contention, the data processing circuits (44) and (45)
43) The data processing circuit (44) stores the output of the data processing circuit (43) in the memory once, and then reads the data from the memory.
, (45) and then E (dotted arrow in Fig. 6(a)).

In other words, when performing vibration line processing of 4 or more stages,
As shown in FIG. 6(b), the Vibration line processing is interrupted every third stage, which has the disadvantage that the processing time is longer than the original Vibration processing shown in FIG. 6(C).

Also, in order to achieve this, it is necessary to install one more image bus than the number of required pipeline stages.
Preparing a large number of image buses in advance has the disadvantage of significantly increasing the amount of hardware, and when expanding the number of image buses, it is necessary to prepare image memory and change the connections between other data processing circuits and the image bus. There was a problem.

This invention was made to solve the above-mentioned problems, and it is not necessary to change the connections between other image memories, other data processing circuits, and the image bus when expanding, and it improves processing speed. An object of the present invention is to obtain an image processing device capable of performing vibrating processing in any number of stages and in any order.

(Means for Solving the Problems) An image processing device according to the present invention includes an image input circuit that multi-values an image signal from a television camera for each pixel and sends it to an image bus; an image memory that stores the image data, a data processing circuit that performs data processing on the image data from the image bus, and outputs the result to the image bus, and a display memory that stores and displays the image data from the image bus. An image processing device comprising an image output circuit including an image output circuit, and a CPU that controls the operation of the device via a system bus, the image input circuit, an image memory,
Bus connection control circuits that enable arbitrary connections between data processing circuits, image output circuits, and the image bus are distributed over the image bus, and the image bus that connects the bus connection control circuits is arranged in a ring shape. By configuring it as an image ring bus coupled to the image bus, the connections between the image input circuit, image memory, data processing circuit, and image output circuit and the image bus can be changed, making it possible to perform arbitrary vibration line processing. This is what I did.

(Function) In the present invention, the bus coupling control circuit on the image ring bus is composed of a multiplexer circuit and a latch circuit, and flexibly changes the connection of the image ring bus under control from the CPU. avoid conflicts,
Achieve arbitrary vibe line processing.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
In the figure, (1) is a television camera, (2) is an image input circuit that multi-values the image signal obtained by the television camera (1) for each pixel, and (31) and (32) are image data image memory for storing (41), (42)
is a data processing circuit that performs preprocessing such as density conversion and differentiation at high speed on sequentially sent image data, and sequentially outputs the processing results. Also, (75), (76)
, (77) is an image ring bus for transmitting image data, and (5) is a display memory for storing image data sent from image ring buses (75) to (77) and displaying it on the monitor (6). The image output circuit (8) includes a CPU which controls the entire device via the system bus (9). (101) to (106) C. Image input circuit (2)
), image memories (31), (32), data processing circuits (41), (42), and connections between the image output circuit (5) and the image ring buses (75) to (77) are connected to the CP.
A bus connection control circuit that changes arbitrarily by control from U (8), and these bus connection control circuits (101) to (106) are connected to the image ring bus (75).
(77), and each bus connection control circuit is connected to the left and right bus connection controls to form a ring-connected image ring bus.

Figure 2 shows the bus coupling control circuit (10n) (n
is an example of the internal structure of a natural number). In the figure, (+1
1) - (116) are respectively image ring buses (75a) -
Latch circuits (77a) and (75b) to (77b) hold input data, and (117) to (119) hold manual data from the image input circuit, image memory, data processing circuit, or image output circuit, respectively. The latch circuits (121) to (12[i) are each latch circuit (114
) to (Ilfi), one corresponding output of (111) to (113) and three latch circuits (117) to (119)
A multiplexer circuit (127) to (129) each selects one of the four outputs of the latch circuit (127) to (129).
Multiplexer circuits (131) to (136) each hold the outputs of the multiplexer circuits (121) to (126), and the image ring bus (75a) selects any one of the six outputs (11) to (11B). ) ~(77a)
(75b) to (77b), the latch circuit outputs to (77b), (
137) to (139) are multiplexer circuits (12
7) shows a latch circuit that holds the outputs of (129) and outputs them to an image input circuit, an image memory, a data processing circuit, or an image output circuit; ), the image ring bus (75) to (7
7) and image input circuit, image memory section, data processing circuit,
It becomes possible to arbitrarily change the bus connection with the image output circuit.

Next, the operation will be explained with reference to FIG. For explanation,
5 units of data processing circuits (41) to (45), image input circuit (2), image memory (31), 7 units of bus connection control circuits (101) to (1,07), image ring bus (75) - (77) shows the case of three systems. FIG. 3 shows data processing circuits (41) to (45) for image data output from the image input circuit (2) (referred to as processing A).
) An image ring bus, an image input circuit, an image memory, and a data processing circuit when performing five stages of vibrating processing of processing C to G and storing the processing results in the image memory (31) (indicated as processing B). It is a figure showing a state of combination with , and shows the vibe line processing performed in the order of processing A-C-F-D-G-E-B. The image data output from the image input circuit (2) is sent to the bus connection control circuit (101).
~ (103) to the data processing circuit (41) and subjected to processing C. Next, the output of process C is sent to the data processing circuit (44) via bus connection control circuits (103) to (106), and process F is executed. As shown in the figure below, the image ring bus and bus coupling control circuit (
101) to (107), the data processing circuit (42)
.

Connect and process (45) and (43) in order, execute G and E, and store the processing result of process E in the image memory (31) to avoid contention on the image ring bus and achieve vibe line processing. do.

Here, the image input circuit (2) may be an image memory, and the image memory (31) may be an image output circuit. Furthermore, the arrangement of the image input circuit, image memory, data processing circuit, and image output circuit can be freely arranged, and the three-system image ring bus allows any five stages of vibration line processing to be executed. In other words, the path from the data supply unit to any two data processing circuits is configured using one system of image ring bus (processing path A-C-F in Figure 3), and the output of the processing result is the next arbitrary path. The path passing through the two data processing circuits is configured using the following image ring bus system (the third
Processing FDG route in the figure). Finally, by configuring a path for the output of the processing result to the next data processing circuit and data storage using the last system of image ring buses, the route between the data supply section and the data storage is established. 5 in any order
Achieve stage vibration line processing. Note that in FIG. 3, broken lines indicate unused image ring buses. Also,
Even in the conventional example, if the number of image buses is six, it is possible to perform five-stage pipeline processing in any order, and it is not possible to support vibration-line processing with six or more stages.However, in the present invention, the data processing circuit is If they are lined up, it becomes possible to process any number of Vibration lines with one system of image ring buses, so it is possible to handle Vibration line processing of six or more stages, although not in any arbitrary order. In addition, the data processing circuit, image memory, etc. can be expanded and moved by adding a bus connection control circuit, and the bus connection control circuit can connect the image ring buses and transfer image data from one image ring bus to the other. By sending the image to the image ring bus as well as to the image memory unit, it becomes possible to store the intermediate results of the Vibration processing in the image memory, thereby creating an image processing device that is highly expandable and flexible. I can do it.

Note that in the above embodiment, the bus connection control circuit is configured with a latch circuit and a multiplexer circuit so that all bus connections can be made;
By using a circuit whose logical formula was created in
It is also possible to reduce the amount of hardware by making only the bus connections necessary for processing as appropriate based on the commands from (a).

FIG. 4 is a diagram showing an example of the configuration of this internal structure variable type bus connection control circuit, and shows the internal configuration of the bus connection control circuit when performing the vibe line processing shown in FIG. 3.

FIG. 4(a) shows the data processing circuit (43) in FIG.
) is a diagram showing the internal configuration of the bus coupling control circuit (105) connected to the image ring bus (75a), which sends human power from the image ring bus (75a) to the image ring bus (75b) via the latch circuits (1111) and (1341). , input from the image ring bus (76b) to the latch circuit (1151) (1
321) to the image ring bus (76a),
The human power from the image ring bus (77b) is transferred to the latch circuit (1
161), the data processing circuit (4) via (1391)
3), and the human power from the data processing circuit (43) is sent to the image ring bus (77a) via the latch circuits (1171) and (1331). Only the bus connections necessary for the process are made. It is. (:PI
J (8) controls the internal configuration of the bus coupling control circuits (101) to (107) to the fourth
If the bus connections necessary for processing are made in the same manner as shown in FIG. 3(a), vibe line processing in any order can be realized, and the same effects as in the above embodiment can be achieved. In addition, Fig. 4 (a
) In the method shown in
Since the circuit whose logical formula was created in M is used, when changing the internal structure, it is necessary to rewrite the data for creating the internal structure for each bus connection control circuit, which has the drawback that it takes time to change. A bus connection control circuit having the internal structure shown in b) may be used to shorten the change time.

The bus coupling control circuit shown in FIG.
In contrast to the one shown in Figure (a), the latch circuit (1111)
, (1171) is selected and the latch circuit (134
1), the multiplexer circuit (1241) that outputs the output, and the latch circuit (, (1151), (1171)),
[(ttat).

(1171)], [(tut), (xlsl),
(hat) Select one of each output from the latch circuit (
1321), (1331).

(1391), multiplexer circuits (12
21) (1231) and (1291) are added, and the connection form can be changed by controlling the selection in the multiplexer circuit.

In the vibe line processing shown in FIG. 3, the direction of data flow on the image ring buses (75) to (77) for each bus connection control circuit is constant; ) in Figure 4(b).
Even if the structure shown in FIG. 1 is used and the selection in the multiplexer circuit is controlled by the CPU (8), the same effects as in the above embodiment can be obtained. Furthermore, since only one change is required, the change time can be shortened.

Further, in the above embodiment, three image ring buses are used to perform one type of processing per data processing circuit, but depending on the processing content, multiple image ring buses may be used.
A single data processing circuit may be configured to include a plurality of processes.

〔Effect of the invention〕

As described above, according to the present invention, the bus connection control enables arbitrary connection between the image input circuit, image memory, data processing circuit, and image output circuit and the image ring bus connected in a ring shape. Since the circuits are distributed on the image ring bus and configured to avoid bus contention, it is possible to add image memory, data processing circuits, etc. by adding a bus coupling control circuit, and it is possible to use them. The flexible pipeline IA process that was
This has the effect of reducing processing time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an image processing device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the internal configuration of the bus coupling control circuit, and FIG. 3 is a block diagram showing the internal configuration of the bus coupling control circuit. FIG. 4(a) and 4(b) are block diagrams showing the configuration of a bus coupling control circuit with a variable internal structure, and FIG. 5 is a block diagram showing the configuration of a conventional image processing device. 6A and 6B are explanatory diagrams illustrating problems in vibrating line processing in conventional image processing apparatuses. (1) is a television camera, (2) is an image input circuit, (3)
, (31), (32) are image memories, (4)
, (41) to (45) are data processing circuits, (5) is an image output circuit, (6) is a monitor, (71) to (74) are image buses, (75) to (77) are image ring buses, (8)
is the CPU (9) is the system bus, (10) is the bus coupling control circuit, (111) to (119), (
131)~(139), (1111)~(1151
) , (1161) (1161) (1171) , (
1321) , (1331) , (1341) ,
(1391) is a latch circuit, (121) to (129)
, (1221) , (1231) , (124
1>(1291) is a multiplexer circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] An image input circuit that multi-values the image signal from the TV camera for each pixel and sends it to the image bus, an image memory that is connected to the image bus and stores image data, and data processing for the image data from the image bus. a data processing circuit that outputs the processed results to the image bus, an image output circuit that includes a display memory for storing and displaying image data from the image bus, and a CP that controls the operation of the device via the system bus.
In an image processing device configured with U, a bus connection control circuit is provided on the image bus to enable arbitrary connections between the image input circuit, image memory, data processing circuit, and image output circuit and the image bus. The image input circuit, image memory, data processing circuit, and image output circuit can be connected to the image input circuit, image memory, data processing circuit, and image output circuit by configuring the image bus connecting the bus connection control circuits as an image ring bus. An image processing device characterized in that the connection between the image processing device and the image processing device can be changed to enable arbitrary pipeline processing.