JPH0377309A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent that an alignment mark on a wafer cannot be used during a wafer treatment process by a method wherein an alignment mark having a recessed or protruding difference in level is formed on the surface of an insulating film and at least two processes are included as processes to execute a mask alignment operation by using the alignment mark. CONSTITUTION:An insulating film 14 whose surface is flat is formed in a region A, used for a mask alignment operation, on the surface of a substrate 11; an alignment mark 15 having a recessed or protruding difference in level is formed on its surface. Impurity ions used to form a source and a drain are implanted at a high dose by using the alignment mark 15 and by making use of a resist pattern 16 as a mask. However, the SiO2 film 14 acts as a mask even in a part where the resist pattern 16 does not exist, and the impurity ions are not implanted into the Si substrate 11. After that, a heat treatment is executed in order to restore a crystal defect produced in a chip region C by this ion implantation; a new difference in level is not produced in the mask alignment region A. Consequently, the alignment mark 15 can be used in the mask alignment region A even in a posterior process.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, particularly a method for forming an alignment mark for automatic mask alignment, it is possible to prevent an alignment mark on a wafer from becoming unusable in a wafer processing process, and to eliminate the need for an alignment mark. The purpose is to provide a method of manufacturing a small number of semiconductor devices, and the method includes a step of forming an insulating film with a flat surface in a region used for mask alignment on the surface of a substrate, and a step of forming a concave or convex step on the surface of the insulating film. The method includes a step of forming an alignment mark, and further includes at least two steps of performing mask alignment using the alignment mark.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming alignment marks for automatic mask alignment.

In the W manufacturing process of semiconductor devices, a mask or reticle (
When patterns (hereinafter referred to as masks) are sequentially transferred onto a wafer, it is necessary to accurately overlay the next pattern on the existing pattern on the wafer, so alignment marks are provided on both the mask and the wafer. The specifications of alignment marks vary depending on the model of the mask alignment equipment used, and some marks become unusable as alignment marks during the process. This requires a considerable amount of space. This alignment mark is usually provided in a scribe area, but since this scribe area is used not only for mask alignment but also for providing a process check pattern, providing a large number of alignment marks will result in a lack of space. Therefore, areas of space required for mask alignment are desired.

[Conventional technology]

First, a general automatic mask matching method will be briefly explained using the second drawing. An alignment mark 1a with a convex or concave step is provided on the upper surface of the wafer l, and an alignment mark 2a made of a thin chromium film is provided on the lower surface of the photomask substrate 2. Laser light is emitted from above the photomask substrate 2. The beam is irradiated (scanned), and the scattered light generated by diffuse reflection at the edges of each alignment mark la and 2a is captured as a signal.The relative position of the wafer 1 and the photomask substrate 2 is calculated from this signal, and the result is Based on this, the wafer 1 or the photomasks Mvi, 2 are moved to correct this relative position. Therefore, in the mask alignment area A of the wafer 1 (the area where the laser beam can be irradiated (scanned)), there must be no step other than the alignment mark 1a on the surface.

Next, the conventional process of forming and using alignment marks will be explained with reference to FIG. FIGS. 3(a) to 3(f) are schematic cross-sectional views showing an example of a conventional alignment mark formation and usage process. In order to avoid complicating the wafer processing process, the alignment mark is formed using the wafer processing process for the chip area as much as possible, so the alignment mark forming process varies somewhat depending on the type of device. This figure 3 shows the mask alignment area in the scribe area B (see figure 2) using the process of forming the gate electrode in the chip area C (see figure 2) in the manufacturing process of the St gate MO3 integrated circuit. This shows the case where an alignment mark is formed at A (see FIG. 2).

Figure 3(a) shows Si used as a mask for selective oxidation in the field oxide film formation process before the gate electrode formation process.
This is a state in which Si, N, and a film 13 are deposited on the substrate 11 (
5ift film 1 between Si substrate 11 and Si3N film 13
2 is an ultra-thin pad SiO□ film). In the mask alignment area A (see Figure 2), no opening is provided in this 5isN film 13, so no SiO□ film is formed in the next oxidation treatment.Next, this Stun, n13 is etched with C phosphoric acid. FIG. 3(b) shows the state after removal by wet etching, etc.). In the subsequent gate electrode formation process, a gate oxide film is formed by oxidation treatment, and then CVD
A gate electrode is formed by growing polycrystalline St by a method and patterning by photoetching.Using this process, an alignment mark 25 (width 2 μm) is formed in a mask alignment area A as shown in FIG. 3(C). , a protrusion of polycrystalline Si with a height of about 4000 Å) is formed (5 int in the same figure).
The film 24 was formed during the gate oxidation process).

This alignment mark 25 is used for mask alignment in the next source/drain forming step. FIG. 3(d) shows a state in which photoresist is applied in the source/drain forming process, mask alignment is performed, and then exposure and development are performed. A resist pattern 16 is formed in the shaded area of the alignment mark 2a in FIG. In this state (using the resist pattern as a mask) impurity ions (As, P, etc.) are implanted at a high dose (10 Is/cse" or more) to form the source/drain. The state is shown in Figure 3(e). In the figure, 26 is an ion implantation layer.Then, the resist pattern is removed, and heat treatment (annealing) is performed to recover crystal defects caused by this ion implantation.As a result, the surface of the Si substrate 11 is oxidized. However, the growth rate of the oxide film is significantly faster in areas where high-concentration impurity ions have been implanted than in areas where they have not been implanted, so as shown in Figure 3 ( ), Sing
A step is created in the film 27. The position where this new step occurs is within the mask alignment area A.

As described above, there must be no steps other than regular steps (alignment marks) in the same mask alignment area A. Although this new level difference is about 1,000 people lower, the irradiated laser beam will be diffusely reflected at the edge (arrowed part in the figure), giving incorrect position information to the automatic mask alignment device. In this process, even if the alignment mark itself is not damaged, mask alignment cannot be performed in this mask alignment area. Therefore, alignment marks similar to those described above have been previously provided in other areas of both the mask and the wafer, and these marks are used for mask alignment in subsequent steps.

[Problem to be solved by the invention]

However, if there are many processes that cause harmful steps like this, it is necessary to prepare preliminary alignment marks, which causes the problem that a large amount of space in the scribe area must be allocated for mask alignment. there were.

The present invention solves these problems, prevents alignment marks on a wafer from becoming unusable during a high-dose ion implantation process, etc., and provides a method for manufacturing semiconductor devices that requires fewer alignment marks. The purpose is to

(Means for Solving the Problems) According to the present invention, this object includes a step of forming an insulating film with a flat surface in a region used for mask alignment on the surface of a substrate, and a step of forming an insulating film with a flat surface on the surface of the insulating film. forming an alignment mark having a step, and further comprising at least two steps of performing mask alignment using the alignment mark.
This can be achieved by providing a method for manufacturing a semiconductor device characterized by including steps.

[Effect]

If the impurity concentration on the Si substrate surface is high, Si
n, it is known that the growth rate of the film becomes faster. Naturally, the impurity concentration is significantly higher in the areas where high-dose impurity ion implantation was performed, so during subsequent heat treatment (annealing), the SiO
! The film growth rate increases significantly. Therefore, a new level difference will be created.

It has been empirically found that when impurity ion implantation is performed at a high dose of 10''/c- or more, a step occurs that is detrimental to automatic mask alignment.

On the other hand, if the Si0g film is at least 1000 mm thick, it can be used as a mask during ion implantation, so if a 5iQz layer with a sufficient thickness is provided in advance over the entire mask alignment area, it can be used regardless of the presence or absence of a resist pattern. No ions are implanted, and therefore no new step is created by subsequent heat treatment (annealing).

〔Example〕

An embodiment of a semiconductor device according to the present invention will be described with reference to FIG. FIGS. 1(a) to 1(e) are schematic cross-sectional views showing the alignment mark forming/using process d in the embodiment of the present invention. In order to avoid complicating the wafer processing process, the alignment mark is formed using the wafer processing process for the device region as much as possible, so the alignment mark forming process varies somewhat depending on the type of device. This figure 1 is S
In the manufacturing process of the i-gate MO3 integrated circuit, the process of forming the gate electrode in the chip area C (see Fig. 2) is used to form the mask alignment area A (see Fig. 2) in the scribe area B (see Fig. 2). This figure shows the case where an alignment mark is formed in the image (see ).

Figure 1(a) shows S
After depositing the Si3N4 film 13 on the i-substrate 11 by CVD (approximately 1,000 layers), this SiJ film 13 is removed by photoetching over the entire mask alignment area A to create an opening ( The Sing film 12 between the St substrate and the 5isNi film is an ultra-thin pad StO! film.Next, a stow film is applied to the above opening by thermal oxidation treatment.
Figure 1(b) shows the state in which the film 14 is grown (approximately 4,000 to 8,000 people) and the surrounding Si microNall 113 is removed by etching.In the subsequent gate electrode forming process, the gate oxide film is removed by thermal oxidation treatment. After forming the gate electrode, polycrystalline Si is grown using the CVD method and patterned using photoetching to form the gate electrode.
Using this process, alignment marks 15 (width 2 μm, height 400
Forms protrusions of polycrystalline Si that last approximately 10 minutes.

This alignment mark 15 is used for mask alignment in the next source/drain forming step. FIG. 1 (c) shows a state in which photoresist is applied in the source/drain forming process, mask alignment is performed, and then exposure and development are performed. A resist pattern 16 is formed in the shaded area of the alignment mark 2a in FIG. In this state (using the resist pattern as a mask) impurity ions (As, P, etc.) are implanted at a high dose (10"/Cm" or more) to form sources and drains. However, even in areas where there is no resist pattern 16, SiO□ Impurity ions are not implanted into the SN substrate 11 using the mask 11114.

FIG. 1(e) shows the state with the resist pattern removed. Thereafter, by this H-on implantation, chip area C (second
Heat treatment (annealing) is performed to recover the crystal defects that have occurred in the area (see figure), but there is no change in the mask alignment area A (no new step is created), and the state remains as shown in Figure 1 (e). . This is no different from the situation shown in FIG. 1(e).

Therefore, mask alignment can be performed using the alignment mark 15 in this mask alignment area A even in subsequent processes (contact hole forming process, etc.).

As a result, there is no need to separately prepare alignment marks for post-processing (at least for one process), and the corresponding mask alignment area can be effectively used for other purposes (increasing process check patterns). In order to enable the use of more mask alignment devices, more good alignment marks are prepared (, etc.).For each mask alignment area, the width is the same as the scribe area and the length is the same. If it requires a space of 1.5+am and prepares alignment marks for three types of mask alignment devices, the space of 4.5mm in length can be used for other purposes for one time. Become.

Note that there is no dedicated process for forming alignment marks in the above process, and all processes are used for the chip area, so the mask used to form openings in Si and J4'flA in the field oxide film forming process is If you add a pattern to , you will automatically get this result.

The present invention is not limited to the above embodiments, but can be implemented with various modifications. The present invention is effective even in MO8 integrated circuits and bipolar integrated circuits other than Si gates when the process includes an ion implantation process with a high dose of 10''/cm'' or more.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to prevent alignment marks on a wafer from becoming unusable in a wafer processing process, and to provide a method for manufacturing a semiconductor device with a small number of required alignment marks. This greatly contributes to the rationalization of equipment manufacturing.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are schematic cross-sectional views showing the process of forming and using alignment marks in an embodiment of the present invention, and FIG. 2(a)
, (b) are diagrams for explaining a mask alignment method, and FIGS. 3(a) to 3(f) are schematic cross-sectional views showing an example of a conventional alignment mark formation and use process. In the figure, A is the mask alignment area, 1a is the alignment mark, 2a is the photomask alignment mark, and 11 is the Si
13 is a 5fjN4 film, 14 is a sio□ film (insulation 1ii), 15.25 is an alignment mark (step), 16 is a resist pattern, and 27 is a 5f01 film. Figure 1/Cb) #rKanenmasugya's proof of dislike T1=Meno) Business map

Claims (1)

[Claims] Area (A) used for mask alignment on the surface of the substrate (11)
forming an insulating film (14) with a flat surface; and forming an alignment mark (15) having a concave or convex step on the surface of the insulating film (14); 1. A method of manufacturing a semiconductor device, comprising at least two steps of performing mask alignment using a method.