JPH0377342A - Apparatus and method for inspecting semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To normally apply a substrate potential to a substrate by cutting off a ground point of a defective chip by a method wherein probes are erected simultaneously on a plurality of chips and switches such as relays or the like which can be cut off are connected between the probes erected on ground terminals of the chips and ground points of an inspection machine. CONSTITUTION:Probes are erected simultaneously on electrodes of a semiconductor integrated circuit chip 11 and a chip 12 on a wafer 10; they are connected to a voltage source 13 and a voltage source 14 of an inspection machine. A relay 18 is connected between the probe erected on a ground electrode of the chip 11 and a ground point 15 of the inspection machine; a relay 19 is connected between the probe erected on a ground electrode of the chip 12 and the ground point 15 of the inspection machine. When a substrate potential generation circuit 17 of the chip is detective, the relay 19 is opened and the ground electrode can be cut off from the inspection machine; various characteristics of the chip 11 can be inspected accurately in succession.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an inspection apparatus and inspection method for simultaneously inspecting a plurality of semiconductor integrated circuit chips in parallel at the wafer stage.

BACKGROUND OF THE INVENTION As the degree of integration of semiconductor integrated circuits increases year by year, a long time is required for functional testing of semiconductor integrated circuits. Furthermore, the functions have become more complex, and the inspection machines that perform the function inspection have also become more expensive. For this reason, the cost required for functional testing of semiconductor integrated circuits is increasing year by year. As a method for reducing such testing costs, there is a simultaneous parallel testing technique in which a plurality of devices are treated as one device and various test conditions generated by an inspection machine are simultaneously applied to the plurality of devices for inspection.

FIG. 2 shows an inspection method using such a conventional inspection machine. In FIG. 2, probes are placed on the electrodes of semiconductor integrated circuit chips 1 and 2 on the wafer 8 at the same time, and the probe placed on the electrode of chip 1 is connected to the voltage source 3 of the inspection machine. , the probes set up on the electrodes of chips 2 are connected to the voltage source 4 of the inspection machine, and the probes placed on the electrodes of chips 1,
Both ground electrodes of No. 2 are connected to a ground point 5 of the inspection machine. A voltage f1 is simultaneously applied to the chips 1 and 2 from the inspection machine voltage source 3 and the voltage source 4, and the currents of the two chips can be measured at 1-time.

Problems to be Solved by the Invention However, not all of the chips to be measured at the same time are necessarily good chips, and there may be some defective chips. Also, a substrate potential generation circuit 6.7 that makes the substrate potential of the semiconductor integrated circuit more negative than the ground level in order to improve the electrical characteristics.
is incorporated into the semiconductor integrated circuit chip 1.2. The output terminal of this substrate potential generation circuit 6.7 is in direct contact with the impurity diffusion terminal on the substrate, and applies a potential to the substrate. However, if one of the substrate potential generation circuits 6 and 7 of the chip to be measured at the same time is defective, and the output section of the substrate potential generation circuit has a leak or short circuit with the ground point of the chip, the substrate potential generation circuit will not operate normally. Since the chips used in this test are also connected to the substrate, it is difficult to maintain the substrate potential at a normal potential, which poses the problem of not being able to perform proper functional tests.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a method for testing semiconductor integrated circuits at the wafer stage by placing probes on several chips at the same time and placing probes on the ground terminals of the plurality of chips. Simultaneous parallel testing is performed using a testing machine equipped with a switch such as a relay that can disconnect and disconnect the electrical connection between each probe and the ground point of the testing machine.

Due to the working structure, even if there is a defective chip in which the output part of the substrate potential generation circuit and the ground point are shorted in the chip during simultaneous parallel testing, the ground point of the defective chip can be connected from the ground point of the inspection machine. By cutting it off, it becomes possible to properly apply the substrate potential to the substrate.

Example An embodiment of the present invention will be described with reference to FIG.

First, in the figure, probes are placed on the electrodes of the semiconductor integrated circuit chip 11 and the chip 12 on the wafer 10 at the same time. The probes set up on the electrodes of the chip 11 are connected to the voltage source 13 of the testing machine, and the probes set up on the electrodes of the chip 12 are connected to the voltage source 14 of the testing machine. A relay 18 is connected between the probe erected on the ground electrode of the chip 11 and the ground point 15 of the inspection machine,
A relay 19 is connected between a probe placed on the ground electrode of the chip 12 and a ground point 15 of the test machine. During simultaneous parallel testing of chips 11 and 12, relays 18 and 19 are closed. Chip 11 and chip 12 have substrate potential generation circuits 16 and 17, respectively.
Therefore, before performing simultaneous parallel testing, the substrate potential generation circuit of the chip alone is tested. That is, the relay 19 is opened and the substrate potential generation circuit 16 of the chip 11 is inspected, and then the relay 18 is opened and the substrate potential generation circuit 1 of the chip 12 is inspected.
Inspect 7. Chip 11. When both substrate potential generation circuits 16 and 17 of [chip] 2 are good, the relay 18
．． 19 is closed, various characteristics tests of the chips 11 and 12 can be performed simultaneously and in parallel. If the substrate potential generation circuit 17 of the chip 12 is defective, it is possible to open the relay 19 and disconnect the ground electrode of the chip 12 from the testing machine so as not to adversely affect the substrate potential of the chip 11. Then, the chip 11 can be accurately tested for various characteristics.

Effects of the Invention As described above, according to the present invention, even if adjacent chips on a wafer are defective, it is possible to accurately test multiple chips simultaneously in parallel.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram for explaining an embodiment of the present invention, and FIG. 2 is a schematic diagram for explaining a conventional example. ], 2.1.1.12... Semiconductor integrated circuit chip, 8, 10... Wafer 3, 4, 13.14
... Voltage source of the inspection machine, 5, 15... Ground point of the inspection machine, 6, 7.16.17... Substrate potential generation circuit, 18.19... ····relay

Claims (2)

[Claims] (1) The voltage source of the inspection machine is connected to a plurality of probes that are simultaneously erected on each electrode to be inspected of a plurality of chips configured on a wafer, and the plurality of probes are erected on each ground electrode of the plurality of chips. A testing device for a semiconductor integrated circuit, characterized in that a plurality of switches are inserted between the ground point of the testing device and the grounding point of the testing device. (2) The voltage source of the inspection machine is connected to a plurality of probes that are simultaneously erected on each electrode to be inspected of a plurality of chips configured on a wafer, and the plurality of probes are erected on each ground electrode of the plurality of chips. Using a tester with a plurality of switches inserted between the ground point of the tester and the ground point of the tester, first close the plurality of switches one by one in order to test each chip on its own. The substrate potential generation circuits incorporated in the chip are inspected for good or bad, and if all the substrate potential generation circuits of the plurality of chips are good, then all the plurality of switches are closed, and each of the electrodes to be tested of the plurality of chips is inspected. The plurality of chips are tested in parallel by simultaneously applying voltage from the voltage source, and if the substrate potential generation circuit of any chip is defective, only the switch corresponding to the defective chip is opened, and the other switches are opened. A semiconductor integrated circuit testing method characterized by simultaneously testing only non-defective chips in parallel by closing the circuit.