JPH0377464U - - Google Patents

Info

Publication number
JPH0377464U
JPH0377464U JP13744189U JP13744189U JPH0377464U JP H0377464 U JPH0377464 U JP H0377464U JP 13744189 U JP13744189 U JP 13744189U JP 13744189 U JP13744189 U JP 13744189U JP H0377464 U JPH0377464 U JP H0377464U
Authority
JP
Japan
Prior art keywords
film
oxide film
gate insulating
insulating film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13744189U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13744189U priority Critical patent/JPH0377464U/ja
Publication of JPH0377464U publication Critical patent/JPH0377464U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例のゲート絶縁膜に
、酸化膜と窒化膜の2層膜を用いた高耐圧MOS
IC高圧部Pチヤンネルトランジスタの要部断
面図である。第2図は、ゲート絶縁膜に酸化膜の
みを用いた従来のMOS IC高圧部Pチヤンネ
ルトランジスタの要部断面図である。 1……PSG(層間絶縁膜)、2……ポリシリ
コンゲート、3……ゲート酸化膜、4……接合部
、5……フイールド酸化膜、6……N型エピ層、
7……ソース領域、8……ゲート電極、9……ド
レイン領域。
Figure 1 shows a high voltage MOS using a two-layer film of an oxide film and a nitride film as the gate insulating film of an embodiment of this invention.
FIG. 2 is a cross-sectional view of a main part of an IC high-voltage section P-channel transistor. FIG. 2 is a sectional view of a main part of a conventional MOS IC high voltage P channel transistor using only an oxide film as a gate insulating film. 1... PSG (interlayer insulating film), 2... Polysilicon gate, 3... Gate oxide film, 4... Junction, 5... Field oxide film, 6... N-type epi layer,
7... Source region, 8... Gate electrode, 9... Drain region.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ゲート絶縁膜を、酸化膜と窒化膜の2層膜で形
成したことを特徴とするMOS半導体装置。
A MOS semiconductor device characterized in that a gate insulating film is formed of a two-layer film of an oxide film and a nitride film.
JP13744189U 1989-11-28 1989-11-28 Pending JPH0377464U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13744189U JPH0377464U (en) 1989-11-28 1989-11-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13744189U JPH0377464U (en) 1989-11-28 1989-11-28

Publications (1)

Publication Number Publication Date
JPH0377464U true JPH0377464U (en) 1991-08-05

Family

ID=31684597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13744189U Pending JPH0377464U (en) 1989-11-28 1989-11-28

Country Status (1)

Country Link
JP (1) JPH0377464U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002170888A (en) * 2000-11-30 2002-06-14 Hitachi Ltd Semiconductor integrated circuit device and method of manufacturing the same
JP2008258640A (en) * 2008-05-07 2008-10-23 Renesas Technology Corp Semiconductor integrated circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002170888A (en) * 2000-11-30 2002-06-14 Hitachi Ltd Semiconductor integrated circuit device and method of manufacturing the same
JP2008258640A (en) * 2008-05-07 2008-10-23 Renesas Technology Corp Semiconductor integrated circuit device

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