JPH0377533B2 - - Google Patents
Info
- Publication number
- JPH0377533B2 JPH0377533B2 JP7728884A JP7728884A JPH0377533B2 JP H0377533 B2 JPH0377533 B2 JP H0377533B2 JP 7728884 A JP7728884 A JP 7728884A JP 7728884 A JP7728884 A JP 7728884A JP H0377533 B2 JPH0377533 B2 JP H0377533B2
- Authority
- JP
- Japan
- Prior art keywords
- register
- bit
- original data
- flml
- determination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は多数ビツトの原データについて
FLML命令によるビツト“１”位置を短時間に
検出できるFLML命令処理方式に関する。[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to multi-bit original data.
This invention relates to an FLML instruction processing method that can detect a bit "1" position by an FLML instruction in a short time.
(2) 従来技術と問題点
大型の汎用計算機では原データについて左側か
ら順次に“１”“０”を判定し、最初に“１”と
判定したビツトの位置を求める処理の必要なこと
がある。この処理を行なう命令をFLM命令とい
う。FLMはFind Left Most Oneの略語である。
従来のFLM処理は32ビツト（４バイト）を格納
する汎用レジスタに原データを格納し、レジスタ
の内容について“１”“０”を順次に判定するこ
とであり、本処理では、32ビツト固定の原データ
のみが扱われていた。したがつて処理すべき原デ
ータが32ビツト以上となる場合が多くなつた現在
では、単一命令による32ビツト毎の処理を繰返す
必要があり、そのためデータの格納とリセツトを
繰返す処理時間が無駄となり、またFLM命令に
よる処理として最初に“１”と判定したビツトの
位置を求めるため特別な計算用処理を設けておく
必要があつた。(2) Conventional technology and problems In large general-purpose computers, it may be necessary to sequentially determine whether the original data is "1" or "0" from the left side and find the position of the bit that was determined to be "1" first. . The instruction that performs this processing is called the FLM instruction. FLM is an abbreviation for Find Left Most One.
Conventional FLM processing stores original data in a general-purpose register that stores 32 bits (4 bytes), and sequentially determines whether the contents of the register are ``1'' or ``0''. Only the original data was used. Therefore, now that the raw data to be processed is often 32 bits or more, it is necessary to repeat processing for each 32 bits using a single instruction, which wastes processing time for repeatedly storing and resetting data. In addition, it was necessary to provide special calculation processing in order to obtain the position of the bit that was first determined to be "1" as part of the processing by the FLM instruction.
(3) 発明の目的
本発明の目的は前述の欠点を改善し、記憶装置
上の可変長の原データについてFLML命令を適
用し、短時間に処理できるデータ処理方式を提供
することにある。FLMLとはFind Left Most
One Longの略語である。(3) Object of the Invention The object of the present invention is to improve the above-mentioned drawbacks and provide a data processing method that can process variable-length original data on a storage device in a short time by applying FLML instructions. What is FLML?Find Left Most
It is an abbreviation for One Long.
(4) 発明の構成
前述の目的を達成するための本発明の構成は、
記憶装置に格納されている可変長の原データにつ
いて、格納アドレスと判定すべき範囲長により指
定されるアドレスのデータを判定用レジスタに転
送し、左方のビツトから順次に“１”“０”を判
定すると同時に、“０”の場合に内容を所定値更
新して“０”判定回数を計数するレジスタを設
け、判定用レジスタの内容がすべて“０”のとき
順次格納アドレスを更新して対応する記憶装置の
原データを判定用レジスタに格納し、ビツト
“１”を判定したとき判定回数を計数するレジス
タの計数値により最も左方にあるビツト“１”の
位置を求めることである。(4) Structure of the invention The structure of the present invention to achieve the above object is as follows:
Regarding the variable length original data stored in the storage device, the data at the address specified by the storage address and the range length to be determined is transferred to the determination register, and the bits are sequentially set to "1" and "0" from the left side. At the same time, a register is provided to update the contents to a predetermined value in the case of "0" and count the number of "0" determinations, and when the contents of the determination register are all "0", the storage address is sequentially updated. The original data of the storage device to be determined is stored in a determination register, and when a bit "1" is determined, the position of the leftmost bit "1" is determined based on the count value of the register that counts the number of determinations.
(5) 発明の実施例
第１図は本発明の一実施例を示す構成図で
MEMは原データの格納されている記憶装置、
CPUは中央処理装置を示し、DTは原データ、
FLPはFLML命令実行部、Ｒ１〜Rnは汎用レジ
スタ、r1，r2，…rnはFLML命令実行部のレジス
タ、TLはデータ伝送路を示す。今中央処理装置
CPUに対しFLML命令が
FLML R1 R2 Ｄ（R3）
の形式で与えられたとすると、FLML命令実行
部FLPは次のように動作する。(5) Embodiment of the invention Figure 1 is a configuration diagram showing an embodiment of the invention.
MEM is a storage device where original data is stored.
CPU indicates the central processing unit, DT is the original data,
FLP is an FLML instruction execution unit, R1 to Rn are general-purpose registers, r 1 , r 2 , . . . rn are registers of the FLML instruction execution unit, and TL is a data transmission path. now central processing unit
If an FLML instruction is given to the CPU in the format FLML R1 R2 D(R3), the FLML instruction execution unit FLP operates as follows.
(イ) Ｒ３で示されるアドレスにオフセツト値Ｄを
加え、その値をアドレスレジスタr2に設定す
る。(a) Add offset value D to the address indicated by R3 and set that value in address register r2 .
(ロ) Ｒ２で示される原データの長さを範囲用レジ
スタr3に設定する。(b) Set the length of the original data indicated by R2 in the range register r3 .
(ハ) カウンタレジスタr4に零を設定する。(c) Set counter register r4 to zero.
(ニ) アドレスレジスタr2で示される記憶装置の内
容１バイトをビツト捜査レジスタr1に転送す
る。(d) Transfer one byte of the contents of the storage device indicated by address register r2 to bit search register r1 .
(ホ) ビツト捜査レジスタr1の左側から順次にビツ
トが“０”か“１”かを判定する。(e) Determine whether the bits are "0" or "1" sequentially from the left side of bit investigation register r1 .
(ヘ) もしビツトが“０”であればカウンタレジス
タr4を「１」歩進し、ビツト判定を続行する。(f) If the bit is "0", counter register r4 is incremented by "1" and bit determination is continued.
(ト) ビツト捜査レジスタr1の全データ（８ビツ
ト）の捜査が終了するとアドレスレジスタr2を
「１」歩進し、範囲用レジスタr3を「１」減算
する。このとき範囲用レジスタr3が「０」でな
ければ(ニ)に戻る、もし範囲用レジスタr3が
「０」のときは、コンデイシヨンコードCCに捜
査した全ビツトが“０”の旨の値CC＝“０”を
設定して処理を終了する。(g) When the investigation of all data (8 bits) in the bit investigation register r1 is completed, the address register r2 is incremented by "1" and the range register r3 is subtracted by "1". At this time, if the range register r 3 is not "0", the process returns to (d). If the range register r 3 is "0", the condition code CC indicates that all bits investigated are "0". The value CC=“0” is set and the process ends.
(チ) 捜査レジスタr1におけるビツトが“１”とな
つているときは、カウンタレジスタr4の値をレ
ジスタR1に転送し、コンデイシヨンコードCC
＝“１”として処理を終了する。(h) When the bit in investigation register r1 is “1”, transfer the value of counter register r4 to register R1 and set condition code CC.
="1" and the process ends.
以上の動作をフローチヤートで示すと第２図の
ようになる。この処理で判るように単一の
FLML命令により原データの多数ビツトについ
て処理することができる。従来は単一の命令によ
り処理できるビツト長が限られていた。 The above operation is shown in a flowchart as shown in FIG. As you can see from this process, a single
FLML instructions can process multiple bits of raw data. Conventionally, the bit length that could be processed by a single instruction was limited.
(6) 発明の効果
このようにして本発明によると長いデータであ
つても、より短時間に捜査することができる。例
えばページ単位のリアル空間を論理空間に割当て
たか否か、デイスク上の論理的に区切つた空間が
使用中か否か等ビツトマツプとして管理されるデ
ータに対し、FLML命令を適用することでシス
テムの性能向上をはかることができる。(6) Effects of the invention In this way, according to the present invention, even long data can be investigated in a shorter time. For example, by applying FLML instructions to data managed as bitmaps, you can improve system performance by checking whether real space in units of pages has been allocated to logical space, whether logically divided space on disk is in use, etc. You can make improvements.
第１図は本発明の一実施例の構成を示す図、第
２図は第１図の動作フローチヤートを示す。
MEM……記憶装置、DT……原データ、CPU
……中央処理装置、FLP……FLML命令実行部、
R1〜Ro……汎用レジスタ、r1，r2，…ro……
FLM命令実行部のレジスタ、TL……データ伝送
路、CC……コンデイシヨンコード。
FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a flowchart of the operation of FIG. 1. MEM...Storage device, DT...Original data, CPU
... central processing unit, FLP ... FLML instruction execution unit,
R 1 ~ R o ... General purpose register, r 1 , r 2 , ... r o ...
FLM instruction execution unit register, TL...data transmission path, CC...condition code.
Claims (1)
について、格納アドレスと判定すべき範囲長によ
り指定されるアドレスのデータを判定用レジスタ
に転送し、左方のビツトから順次に“１”“０”
を判定すると同時に、“０”の場合に内容を所定
値更新して“０”判定回数を計数するレジスタを
設け、判定用レジスタの内容がすべて“０”のと
き順次格納アドレスを更新して対応する記憶装置
の原データを判定用レジスタに格納し、ビツト
“１”を判定したとき、上記判定回数を計数する
レジスタの計数値により最も左方にあるビツト
“１”の位置を求めることを特徴とするFLML命
令処理方式。1 Regarding the variable length original data stored in the storage device, transfer the data at the address specified by the storage address and the range length to be judged to the judgment register, and sequentially change the bits from the left to “1” and “0”. ”
At the same time, a register is provided to update the contents to a predetermined value in the case of "0" and count the number of "0" determinations, and when the contents of the determination register are all "0", the storage address is sequentially updated. The original data of the storage device is stored in a determination register, and when the bit is determined to be "1", the position of the leftmost bit "1" is determined based on the count value of the register that counts the number of times of determination. FLML instruction processing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7728884A JPS60220423A (en) | 1984-04-17 | 1984-04-17 | Processing system of flml instruction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7728884A JPS60220423A (en) | 1984-04-17 | 1984-04-17 | Processing system of flml instruction |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60220423A JPS60220423A (en) | 1985-11-05 |
| JPH0377533B2 true JPH0377533B2 (en) | 1991-12-10 |
Family
ID=13629684
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7728884A Granted JPS60220423A (en) | 1984-04-17 | 1984-04-17 | Processing system of flml instruction |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60220423A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014033866A1 (en) | 2012-08-29 | 2014-03-06 | 富士通株式会社 | Communication device, system, and communication method |
| JP6540841B1 (en) | 2018-02-27 | 2019-07-10 | 富士通株式会社 | Arithmetic processing device, information processing device, information processing method, and program |
-
1984
- 1984-04-17 JP JP7728884A patent/JPS60220423A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60220423A (en) | 1985-11-05 |
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