JPH0377665B2 - - Google Patents

Description

[Detailed Description of the Invention] Technical Field of the Invention The present invention relates to a semiconductor integrated circuit, particularly a semiconductor integrated circuit in which an analog circuit and a digital circuit are formed on the same substrate, and improves the method of applying a substrate potential using aluminum wiring. .

Conventional technology and problems In order to provide the lowest potential to the substrate in a semiconductor integrated circuit in which analog circuits and digital circuits are mixed on one chip, conventionally, as shown in Fig. 1, the negative conductor of the external power supply or the negative voltage generating circuit 1 is used. Apply voltage -V from the pad 3 of the p-type silicon semiconductor substrate (bulk) 2 to the Al (aluminum) wiring 4A, 4D extending from the pad to the digital circuit side and the analog circuit side.
Generally, the aluminum wiring is brought out and brought into contact with the substrate 2 in the contact area shown with diagonal lines. In the figure, A is an analog circuit,
D is a digital circuit. In the figure, contact between the aluminum wiring and the board is made only on the analog circuit A side, but this is insufficient to apply the minimum potential to the board on the digital circuit D side, so a contact window is opened and the aluminum wiring is connected to the board on the analog circuit A side. It is also necessary to connect the 4D and the board 2. However, in this method, since a substrate resistance R exists between the contact regions of the wirings 4A and 4D with the substrate, there is a drawback that potential fluctuations in one circuit are transmitted to the other. Further, it is preferable to reduce the impedance of the ground wiring, and for this purpose, the widths of the wirings 4A and 4D are set wide, but this causes the following problem. That is, if these wirings are wired to the emitters E of the npn transistors 5D and 5A as shown in FIG. 2, there is a risk that the pn junction between the emitters E and the bases B will be destroyed. In other words, when the wiring 4D is brought into contact with the emitter region E of the transistor 5D, the wiring 4D becomes pure Al.
, the silicon in the emitter region E is connected to the wiring 4.
conversely, the aluminum of wiring 4D enters the silicon of area E, and the aluminum in the contact area
-Create a eutectic alloy of Si. If the emitter region is shallow, this eutectic alloy layer extends to the base-emitter junction, making the junction leaky and deteriorating the characteristics of the transistor. This phenomenon can be thought of as Al being supplied from the wiring side and a corresponding amount of Si being supplied from the substrate side.If the wiring is thin, the Al supply is insufficient, so juncture damage is less likely to occur, and the wiring is made of pure Al. This can also be prevented by using Al containing Si. Therefore, it is possible to form a large-area sub-contact window 6D to bring the Al wiring 4D into contact with the underlying p-type substrate 2, and to supply sufficient silicon into the Al from there, which is an effective countermeasure. It is. Similar means for Al wiring 4A
It is possible to do this on the side, but this would cause the problem described in Figure 1, so the same method cannot be used.

Purpose of the Invention The present invention improves the above points and makes it possible to apply the lowest potential to multiple locations on a semiconductor substrate of an integrated circuit in which analog circuits and digital circuits are mixed without any problem using pure Al wiring. This is what we are trying to do.

Structure of the Invention The present invention provides a semiconductor integrated circuit in which aluminum wiring provides the lowest potential at multiple locations on a silicon semiconductor substrate, in which one of the aluminum wirings is directly connected to the semiconductor substrate, and the other wiring is of a conductivity type opposite to that of the substrate. The present invention is characterized in that a dummy land is created and connected to the land, and this will be explained in detail below with reference to the illustrated embodiment.

Embodiment of the Invention FIG. 2 is a diagram showing an embodiment of the present invention, in which 7 is an n-type dummy land added according to the present invention. This is made by diffusing or ion-implanting n-type impurities into the frame 7 of the p-type semiconductor substrate 2. 6A
is the n-type land 7 drilled in the insulating film on the substrate surface.
This is a large-area sub-contact window with the Al wiring 4A, where the wiring 4A makes ohmic contact with the substrate and is further connected to the emitter region E of the npn transistor 5A. With this configuration, a diode D having the illustrated polarity is formed between the p-type substrate 2 and the n-type land 7, so that the contact regions 6D, 6A
Even if the two wires are connected by a resistor R, the connection is cut off by the floating diode D, and a change in the potential of the wire 4A will not be transmitted to the other wire 4D, or vice versa. . However, since this diode D is equivalently a capacitor, at high frequencies the contact areas 6D and 6A are connected by the resistor R and the diode D, which looks like a capacitor, so it is not effective, but in the low frequency range it is sufficient for practical use. There is sex.

Of course, even if the land 7 is n-type, it is still a silicon layer, so silicon is sufficiently implanted into the Al wiring 4A from the n-type land 7, and the junction between the base and emitter of the transistor 5A is formed. It does not deteriorate the characteristics. Figure 3 is a diagram explaining the silicon supply situation on the digital circuit side.
Silicon is sufficiently supplied into the aluminum wiring 4D through the large-area sub-contact window 6D (the arrow indicates this), so that the exchange of Al and Si at the contact portion between the wiring 4D and the emitter E is minimal. There is little risk of E-B juncture failure.

Effects of the Invention As described above, according to the present invention, on the one hand, a dummy land is provided and an Al
Since the wiring is made in contact, the pn junction characteristics of the device will not deteriorate even in integrated circuits that make contact with the Al wiring at multiple locations on the board, and the analog system and digital system can be completely separated. I can do it.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a semiconductor device in which an analog circuit and a digital circuit are integrated on one chip, FIG. 2 is a plan view showing an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation. In the figure, 2 is a semiconductor substrate, 4A and 4D are Al wiring,
5A and 5D are transistors, 6A and 6D are sub-contact windows, 7 is a dummy land, A is an analog circuit, and D is a digital circuit.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit in which the lowest potential is applied to multiple locations on a silicon semiconductor substrate using aluminum wiring, one of the aluminum wirings is directly connected to the semiconductor substrate, and the remaining aluminum wiring is of a conductivity type opposite to that of the substrate. A semiconductor integrated circuit characterized in that a dummy land is formed and connected to the land. 2. A patent characterized in that an analog circuit is formed on one side of a semiconductor substrate and a digital circuit is formed on the other side, and aluminum wiring is connected to the substrate and dummy lands formed thereon on the analog circuit side and the digital circuit side. A semiconductor integrated circuit according to claim 1.