JPS5986253A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable to apply the lowest voltage to a semiconductor substrate of an integrated circuit in which an analog circuit and a digital circuit are mixed by pure aluminum wirings without fail by contacting wirings for applying the lowest voltage by providing a dummy land at one side. CONSTITUTION:An n type dummy land 7 is formed by diffusing or ion implanting n type impurity on a p type semiconductor substrate 2. Wirings 4A are ohmically contacted with the substrate through a subcontacting window 6A of large area with the land 7 and aluminum wirings 4A, and connected to the emitter region E of an n-p-n type transistor 5A. In this manner, a diode D is formed between the substrate 2 and the land 7, and even if a resistor R is connected between the contacting regions 6D and 6A, the connection is interrupted by a diode D of floating state, and the variation in the voltage of the wirings 4A is not transmitted to the wirings 4D.

Description

[Detailed Description of the Invention] Technical Field of the Invention The present invention relates to a semiconductor integrated circuit, particularly a semiconductor integrated circuit in which an analog circuit and a digital circuit are formed on the same substrate, and improves the method of applying a substrate potential using aluminum wiring. .

Conventional technology and problems In order to provide the lowest potential to the substrate in a semiconductor integrated circuit in which analog circuits and digital circuits are mixed on one chip,
As shown in the figure, the voltage -V from the negative side conductor of the external power supply or the negative voltage generation circuit 1 is applied to the pad 3 of the p-type silicon semiconductor substrate (bulk) 2, and from this band to the digital circuit side and the analog circuit side. AJ (aluminum) wiring 4
Generally, A and 4D are drawn out and the aluminum wiring is brought into contact with the substrate 2 at the contact area shown with diagonal lines. In the figure, A is an analog circuit and D is a digital circuit. In the figure, contact between the aluminum wiring and the board is made only on the analog circuit A side, but this is insufficient to apply the lowest potential to the board on the digital circuit side, so a contact window is opened and the aluminum wiring 4D is connected. It is also necessary to make a connection between the board 2 and the board 2. However, this method has a drawback that potential fluctuations in one circuit are transmitted to the other circuit because a substrate resistance R exists in the amount of contact between the wirings 4A and 4D with the substrate. It is also preferable to lower the impedance of the ground wiring, so
Although the widths of A and 4D are set wide, this causes the following problems. That is, these wirings are np as shown in FIG.
n) When wired to the emitter E of the transistors 5D and 5A, there is a risk of destroying the pn junction between the emitter E and the base 8. In other words, when the wiring 4D is brought into contact with the emitter region E of the transistor 5D, if the wiring 4D is made of pure Al, the silicon in the emitter region E will enter into the wiring 4D, and conversely, the aluminum in the wiring R4D will enter into the silicon in the region E. , make a eutectic alloy of A#-3i in the contact area. If the emitter-vine region is shallow, this eutectic alloy layer extends to the base-emitter junction, making the junction leaky and deteriorating the characteristics of the transistor. This phenomenon can be thought of as Al being supplied from the wiring side and a corresponding amount of Si being supplied from the substrate side; if the wiring is thin, the AI supply is insufficient, so junction breakdown is less likely to occur; It is also possible to prevent this by using Al containing St. Therefore, it is possible to form a large-area sub-contact window 6D to bring the Al wiring 4D into contact with the underlying p-type substrate 2, and to supply sufficient silicon into A6 from there, which is an effective countermeasure. It is. Similar means A
It is conceivable that the same method could be used on the l wiring 4A side, but this would cause the problem described in FIG. 1, so the same method cannot be used.

Purpose of the Invention The present invention improves the above points and makes it possible to apply the lowest potential to multiple locations on a semiconductor substrate of an integrated circuit in which analog circuits and digital circuits coexist without any problem using pure A4 wiring. This is what we are trying to do.

Structure of the Invention The present invention provides a semiconductor integrated circuit in which the lowest potential is applied to a plurality of locations on a silicon semiconductor substrate using aluminum wiring, in which the aluminum wiring is directly connected to the semiconductor substrate on the one hand;
The other feature is that a dummy land of a conductivity type opposite to that of the substrate is made and connected to the land, which will be described in detail below with reference to the illustrated embodiment.

Embodiment of the invention - FIG. 2 is a diagram showing an embodiment of the invention, in which 7 is an n-type dummy land added according to the invention.

This is made by diffusing or ion-implanting n-type impurities into the frame 7 of the p-type semiconductor substrate 2. 6A is a large-area sub-contact window between the n-type land 7 and the A1 wiring 4A, which is opened in the insulating film on the surface of the substrate. Connected to E. With such a configuration, a diode D with the polarity shown is connected between the p-type substrate 2 and the n-type land 7.
is formed, so even if the contact regions 6D and 6A are connected by the resistor R, the connection is cut off by the floating diode D, and the potential change of the wiring 4A is transmitted to the other wiring 4D, or vice versa. There is no possibility that changes in potential will be transmitted to. However, this diode D is equivalently a capacitor, so at high frequencies, the contact areas 6D and 6A are connected by the resistor R and the diode D, which looks like a capacitor, so it is not effective, but in the low frequency range it is sufficiently practical. There is sex.

Of course, even if the land 7 is n-type, it is still a silicon layer, so silicon is sufficiently implanted into the AJ wiring 4A from the n-type land 7, and the characteristics of the base-emitter junction of the transistor 5A are will not deteriorate.

FIG. 3 is a diagram explaining the silicon supply situation on the digital circuit side. Silicon is sufficiently supplied into the aluminum wiring 4D through the large-area sub-contact window 6D (arrows indicate this), and therefore the wiring 4D The exchange of AI and Si at the contact part between the E-B
There is little risk of junction destruction.

Effects of the Invention As described above, according to the present invention, on the one hand, a dummy land is provided and the AA wiring giving the lowest potential is brought into contact with the dummy land, so that contact is made with the Al wiring at multiple locations on the substrate. Even in such integrated circuits, the pn junction characteristics of the elements are not deteriorated, and analog systems and digital systems can be completely separated.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a semiconductor device in which an analog circuit and a digital circuit are integrated on one chip, FIG. 2 is a plan view showing an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation. In the figure, 2 is a semiconductor substrate, 4A, 4D are Al wiring, 5A,
5D is a transistor, 6A and 6D are sub-contact windows, 7 is a dummy land, A is an analog circuit, and D is a digital circuit. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi Figure 1 Figure 2 Figure 3 D

Claims (1)

[Claims] (11) In a semiconductor integrated circuit that uses aluminum wiring to provide the lowest potential to multiple locations on a silicon semiconductor substrate, one of the aluminum wirings is directly connected to the semiconductor substrate, and the other conductive wire is opposite to the substrate. (2) An analog circuit is formed on one side of the semiconductor substrate and a digital circuit is formed on the other side, and the aluminum wiring is connected to the analog circuit side and the digital circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is connected to the substrate and the dummy lands formed thereon on the circuit side.