JPH03780Y2 - - Google Patents

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a clamp circuit, and is particularly useful in video signal processing circuits, etc., where the DC component is added back to the signal whose DC component has been lost due to capacitive coupling in the transmission path. Regarding a clamp circuit for reproducing.

(Prior Art) FIG. 2 shows a block diagram of an example of a conventionally known feedback type clamp circuit.

In the circuit shown in the figure, 1 is an input terminal to which a signal such as a composite video signal is input, 2 is a signal output terminal, 3 is an input terminal to which a clamp pulse is input,
4 is a level shift circuit, 5 is a comparator, 6 is a reference voltage source, and 7 is a clamp capacitor (capacitor).

The input terminal 1 is connected to the input terminal of a level shift circuit 4, and the output terminal of this level shift circuit 4 is connected to the input terminal of a comparator 5, while being connected to the output terminal 2. Further, a reference voltage source 6 and a clamp pulse input terminal 3 are connected to the comparator 5, while
The output terminal of the comparator 5 is feedback-connected to the level shift circuit 4 and is further grounded via a clamp capacitor 7.

The above conventional circuit relates to a clamp circuit used in a video signal processing circuit. In the case of this circuit, a clamping operation is performed so that the DC level of the pedestal portion of the input composite video signal after the synchronization signal having no video component becomes equal to a certain set reference voltage level.

The operation of the clamp circuit shown in Figure 2 is generally well known, so we will explain it here.
The outline will be explained below.

The signal (composite video signal) input from input terminal 1 is sent to output terminal 2 via level shift circuit 4.
At the same time, the signal is input to the comparator 5. In this comparator 5, the input signal which is the output signal of the level shift circuit 4 and the reference voltage arbitrarily set by the reference voltage source 6 are applied during the clamp pulse period (synchronization of the composite video signal) input from the input terminal 3. (a period corresponding to the pedestal portion after the signal), and the error current is output. The capacitor 7 is charged and discharged by this error current, and the capacitor 7 is charged and discharged until the next clamp pulse is input.
The voltage across is maintained. The level shift amount of the level shift circuit 4 is controlled by the voltage across the capacitor 7, and the clamp circuit operates so that the pedestal level of the output signal output to the output terminal 3 becomes equal to the reference voltage.

Further, FIG. 3 shows an actual circuit example corresponding to the conventional clamp circuit shown in FIG. 2. In the figure, the same parts or parts with the same functions as those in FIG. 2 are given the same numbers.

The clamping operation will be explained with reference to FIG. The signal input from input terminal 1 is NPN
It is level-shifted by transistor Q ₁ and resistor R ₁ , and is output from output terminal 2, and at the same time, PNP
It is configured to be input to the base of transistor _Q3 .

On the other hand, the PNP transistor Q ₃ and the PNP transistor Q ₄ are configured in a differential type, and the base of the transistor Q ₄ is connected to a reference voltage source 6 consisting of a variable resistor R ₆ . Also, transistor Q ₃
The collector of is connected to the collector of transistor _Q4 via a current mirror circuit (consisting of NPN transistors _Q7 and _Q8 ). Furthermore, the collector of the transistor Q ₄ is connected to one end of the capacitor 7, and at the same time, a current source (NPN transistor Q ₂ , resistor R ₂ ) forming the level shift circuit 4 is connected to the collector of the transistor Q 4 .
Of which transistor Q is connected to the base of ₂ .

Further, a clamp pulse is inputted from the input terminal 3. And when inputting clamp pulse, NPN
Transistor Q ₉ turns on, transistor Q ₃ ,
Current flows through the differential amplifier consisting of Q ₄ via a current mirror circuit (PNP transistors Q ₅ and Q ₆ ).

On the other hand, when the clamp pulse is not input, transistor Q ₉ is turned OFF, and transistors Q ₃ ,
No current flows through the differential amplifier consisting of _Q4 .

Here, in this circuit example, the transistor
Consider the case where the signal DC component at the base of Q ₃ (ie, the base voltage of transistor Q ₃ ) is lower than the reference voltage at the base of transistor Q ₄ (ie, the base voltage of transistor Q ₄ ).

In this case, the current from the current source consisting of transistor Q ₅ and resistor R ₃ flows through transistor Q ₃ and is discharged from capacitor 7 via a current mirror circuit consisting of transistors Q ₇ and Q ₈ .
lower the voltage across the Therefore, the current source (transistor Q ₂ ,
The current in resistor R ₂ ) decreases, and the voltage across resistor R ₁ decreases. Therefore, the output DC level from the output terminal 2 becomes high.

Conversely, when the base voltage of transistor Q ₃ is higher than the base voltage of transistor Q ₄ , current flows through transistor Q ₄ , charging capacitor 7 and increasing the voltage across capacitor 7 . As a result, the current of the current source composed of the transistor Q ₂ and the resistor R ₂ increases, the voltage across the resistor R ₁ increases, and the output DC level decreases.

Through the above-described operation, the circuit loop operates so that the DC component of the output signal from the output terminal 2 becomes equal to the reference voltage set by the reference voltage source 6, and a clamping operation is performed.

(Problem to be solved by the invention) In the conventional clamp circuit shown above, the clamp pulse input to the input terminal 3 is generated by passing the synchronizing signal separated from the composite video signal through a differentiating circuit. I'm making it. Therefore, when the video signal is input normally, the clamp circuit operates without any problem, but for example, in a no-signal state (no video signal is input) and no synchronization signal exists, Since a clamp pulse cannot be generated, the comparator 5 will not operate and the clamp operation will not be performed normally. This caused a problem in that the brightness level on the screen changed significantly when there was no signal, and the quality of the image deteriorated considerably.

(Purpose of the invention) Therefore, the purpose of the invention is to solve the problems of the conventional technology as described above, and to significantly increase the brightness level of the output signal even when there is no synchronizing signal such as when there is no signal. It is an object of the present invention to provide a clamp circuit that improves the quality of an image by keeping it within a certain level without changing.

(Means for solving the problem) In order to achieve the above object, the present invention compares the levels of an arbitrarily set reference voltage and an output signal only during the input period of the clamp pulse, and calculates the error current (voltage). A first comparator that outputs a and a level shift circuit for level shifting an input signal, the output error current (voltage) of the first comparator is negatively fed back to the level shift circuit so that the output signal is always equal to the reference voltage. In the feedback type clamp circuit that clamps and outputs the output signal, the reference voltage and the output signal are respectively input, and the first comparator becomes inoperable so that the DC level of the output signal does not match the reference voltage. a second comparator for detecting that the
and operating means for inputting a pulse signal such as a flyback pulse to the first comparator to operate the first comparator based on the detection signal of the comparator. It is something to do.

(Example) An example of the clamp circuit according to the present invention will be described below with reference to the drawings. In the following figures, the same parts or functional parts as in the previous figures are given the same numbers.

FIG. 1 is a diagram showing an embodiment of the clamp circuit according to the present invention.

In the circuit shown in the figure, 1 is an input terminal to which a signal such as a composite video signal is input, 2 is a signal output terminal, 3 is an input terminal to which a clamp pulse is input,
4 is a level shift circuit, 5 is a comparator (first comparator), 6 is a reference voltage source, 7 is a clamp capacitor (capacitor), 8 is a comparator (second comparator), 9 is a switch circuit, 10 is an input terminal to which a pulse signal such as a flyback pulse (FB pulse) or a DC voltage of a predetermined level is input.

The input terminal 1 is connected to the input terminal of a level shift circuit 4, and the output terminal of this level shift circuit 4 is connected to the input terminal of a comparator (first comparator) 5, and is connected to the output terminal 2, Furthermore, it is connected to a comparator (second comparator) 8. Further, a reference voltage source 6 and a clamp pulse input terminal 3 are connected to the comparator 5, while the output terminal of the comparator 5 is feedback-connected to the level shift circuit 4, and is further connected via a clamp capacitor (capacitor) 7. It is grounded and further connected to one contact terminal of the switch circuit 9. Also,
A reference voltage source 6 is also connected to the comparator 8, and its output terminal is connected to a control terminal of a switch circuit 9. The other contact terminal of the switch circuit 9 is connected to a flyback pulse input terminal 10.

The configuration of the clamp circuit according to the present invention is applicable when a clamp pulse exists (i.e.,
(when the video signal is input normally), the second
Since the clamping operation is exactly the same as that of the conventional clamping circuit shown in FIGS.

Therefore, let us consider a case where no video signal is input and there is no synchronizing signal (no signal state), that is, a case where there is no clamp pulse. In this case, the comparator (first comparator) 5 becomes inoperable, and the DC level of this output signal is not clamped and becomes a level significantly different from the reference voltage. Therefore, in the configuration of the present invention, the output signal of the level shift circuit 4 and the reference voltage of the reference voltage source 6 are connected to the comparator (second
comparator) 8, and if the output signal fluctuates significantly from the reference voltage, the output signal of comparator 8 turns the switch circuit 9 from the OFF state to the ON state.
The switching of the switch circuit 9 is controlled so that the state is reached. Then, a flyback pulse (or a DC voltage at a predetermined level) from the input terminal 10 is inputted to the comparator 5, thereby causing the comparator 5 to operate.

In this way, even in the absence of a clamp pulse, the DC level of the output signal does not fluctuate significantly. Therefore, the quality of the image can be improved. In the case of video equipment such as television receivers (monitors), even when there is no signal (no video signal is input) and there is no synchronizing signal, the horizontal oscillation circuit is free-running oscillation, and the flyback pulse is always present, so the configuration of the present invention operates without any problem.

Further, FIG. 4 shows an actual circuit example corresponding to one embodiment of the clamp circuit according to the present invention shown in FIG.
In the figure, the same parts or parts with the same functions as those in FIG. 1 are given the same numbers.

In the circuit example shown in Fig. 4, when a clamp pulse is present, the NPN transistor _Q12 is connected to the reference voltage source ₆ consisting of the variable resistor R6.
Transistor through the emitter follower circuit of
Voltage V ₁ (reference voltage level) is supplied to the base of Q ₄ , and therefore the output signal DC level at output terminal 2 is V ₁ .

On the other hand, considering the case where there is no clamp pulse, a current source consisting of transistor Q ₅ and resistor R ₃ is connected to a differential amplifier (transistors Q ₃ ,
Since no current is supplied to _Q4 ), clamping operation is no longer performed. In particular, in the case of the circuit example of the present invention, the output signal DC level of the output terminal 2 is determined by the input signal input to the input terminal 1, which is the voltage V ₂ (V ₂ >V ₁ ; V ₁ is the reference voltage level)
The following is output. This output is simultaneously input to the respective bases of NPN transistors Q ₁₄ and Q ₁₅ .

It also forms a differential pair with transistor _Q14 .
The base of the NPN transistor _Q13 is a transistor
A divided voltage V _BE12 of the Q ₁₂ base emitter voltage V _BE is input, and the voltage V ₃ becomes V ₃ = V ₁ + V _BE12 /R ₉ + R ₁₀ × R ₁₀ .

On the other hand, the divided voltage V _D1 of the diode D ₁ is applied to the base of the NPN transistor Q ₁₆ which is a differential pair with the transistor Q ₁₅ , and the voltage V ₄ is as follows: V ₄ = V ₁ − V _D1 /R ₁₁ + R ₁₂ x R ₁₁ .

Now, consider a case where the clamp pulse no longer exists and the DC level V ₂ at the output terminal 2 rises.
At this time, since there is a relationship that the base voltage V _B15 of the transistor Q ₁₅ is higher than the base voltage V _B16 of the transistor Q ₁₆ [V _B15 > V _B16 ], the transistor Q ₁₅ is turned on and the transistor Q ₁₆ is turned off, so that the transistor Q The current of the current source consisting of ₁₇ and resistor R ₁₃ flows through transistor Q ₁₅ .

Also, considering transistor Q ₁₃ and transistor Q ₁₄ , which are a differential pair, the output level V ₂ is V ₂
When the relationship is <V ₃ , transistor Q ₁₃ is ON and transistor Q ₁₄ is OFF, and the current from the current source flows through transistor Q _13. However, when V ₂ > V ₃ , transistor Q ₁₄ is ON, Transistor Q ₁₃
OFF, the current from the current source flows through transistor Q ₁₄ , and then passes through the differential pair of transistors Q ₃ and Q ₄ through a current mirror circuit consisting of PNP transistors Q ₁₀ and Q ₁₁ and resistors R ₇ and R ₈ . flowing into
These act as a comparator, start a clamping operation, and bring the DC level of the output terminal 2 closer to the reference voltage _V1 .

However, again V ₂ <V ₃ [=V ₁ + {V _BE12 / (R ₉ +
Returning to the relationship R ₁₀ )}×R ₁₀ ], transistor Q ₁₃ is turned ON and transistor Q ₁₄ is turned OFF again, current no longer flows through transistors Q ₃ and Q ₄ of the differential pair, and no clamping operation is performed. It disappears.

From the above, the DC level of output terminal 2 is V ₃ [=V ₁ +
It will settle down to the level of {V _BE12 / (R ₉ + R ₁₀ )}×R ₁₀ ].

In addition, the current source (transistor Q ₁₇ , resistor R ₁₃ )
is operated by a flyback pulse (FB pulse) input from the input terminal 10, and has no effect on the clamp operation when a normal synchronizing signal is present.

Furthermore, in the embodiment of the present invention, the case where the DC level V ₂ of the output terminal 2 is V ₂ >V ₁ (V ₁ is the reference voltage level) has been explained, but the case where the output DC level V ₂ is V ₂
<V ₁ , then V ₂ <V ₄ [=V ₁ − {V _D1 / (R ₁₁
+R ₁₂ )}×R ₁₁ ], in the differential pair (transistors Q ₁₅ , Q ₁₆ ), transistor Q ₁₆ turns on and transistor Q ₁₅ turns off, and the current from the current source passes through transistor Q ₁₆ and becomes a current. The signal flows through the mirror circuit (transistors Q ₁₀ , Q ₁₁ , resistors R ₇ , R ₈ ) to the differential amplifier (transistors Q ₃ , Q ₄ ), and starts clamping operation.

In this case, as in the case of V ₂ > V ₁ , the DC level of output terminal 2 is V ₄ [=V ₁ − {V _D1 / (R ₁₁ + R ₁₂ )}×
_R11 ].

In addition, in FIG. 4, _I1 is a constant current source.

Furthermore, in the above embodiment, the flyback pulse that is input when there is no clamp pulse is not limited to this, but is a signal that is locked to the synchronization signal of the input video signal, and is self-excited when there is no signal. Any pulsed signal that oscillates may be used.

FIG. 5 is a block diagram showing an example of a circuit for generating this pulsed signal.

As shown in the figure, a phase-locked loop (PLL) consisting of a phase comparator, a voltage-controlled oscillator (VCO), and an LPF is applied to the synchronization signal that is synchronously separated from the video signal, and the circuit is locked to this synchronization signal. A pulsed signal can be obtained by waveform shaping the VCO output.

(Effects of the invention) As described above, according to the clamp circuit of the invention,
Even when a clamp pulse does not exist, the output DC level will always be around the set reference voltage level V ₁ , and the output DC level will not fluctuate significantly like in the past. Therefore, in the video equipment of television receivers (monitors), it is possible to suppress changes in the brightness level of the image when there is no signal within a certain range, and the quality of the image can be improved. have

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the clamp circuit according to the present invention, Fig. 2 is a block diagram of an example of a conventional feedback type clamp circuit, and Fig. 3 is an actual diagram corresponding to the conventional clamp circuit shown in Fig. 2. 4 is a diagram showing an actual circuit example corresponding to an embodiment of the clamp circuit according to the present invention shown in FIG. 1,
FIG. 5 is a block diagram showing an example of a circuit for generating a pulsed signal. DESCRIPTION OF SYMBOLS 1...Input terminal, 2...Output terminal, 3...Input terminal of clamp pulse, 4...Level shift circuit, 5...Comparator (first comparator), 6...Reference voltage source, 7... ...Clamp capacitance (capacitor), 8
... Comparator (second comparator), 9 ... Switch circuit, 10 ... Flyback pulse (FB pulse)
input terminal.

Claims (1)

[Claims for Utility Model Registration] A first comparator that compares the levels of an arbitrarily set reference voltage and an output signal only during the input period of the clamp pulse, and outputs the error current (voltage); a clamping capacitor connected between the output terminal of the comparator and ground, and a level shift circuit that level-shifts the input signal using the error current (voltage) output from the first comparator. In the feedback type clamp circuit, the output error current (voltage) of the first comparator is negatively fed back to the level shift circuit, and the output signal is clamped and outputted so as to always be equal to the reference voltage. a second comparator to which a reference voltage and the output signal are respectively input, and which detects when the first comparator becomes inoperable and the DC level of the output signal no longer matches the reference voltage; A clamp circuit characterized in that it is provided with operating means for inputting a pulse signal such as a flyback pulse to the first comparator in response to the detection signal of the second comparator to operate the first comparator. .