JPH037963Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and particularly to the structure of a static type semiconductor memory device.

[Conventional technology]

In recent years, the degree of integration and operating speed of semiconductor memory devices have been increasing more and more, but their demands are still high.

In general, a static semiconductor memory device includes a word line, a bit line pair, a power line, and a ground line formed on a semiconductor substrate with an insulating layer interposed therebetween, and each intersection between the word line and the bit line pair to
It is constructed by arranging static type memory cells consisting of MOS transistors. Conventionally, a word line, a power supply line, and a wiring for a gate electrode of a MOS transistor are configured in parallel using a first conductive layer made of, for example, polysilicon, which is formed on a semiconductor substrate with an insulating layer interposed therebetween. The bit line pair and the ground line are formed on the first conductive layer with an insulating layer interposed therebetween, using a second conductive layer made of aluminum, for example, so that the bit line pair and the ground line extend in a direction perpendicular to the extending direction of the word line, etc. It was composed of Therefore, for one memory cell, a total of four polysilicon wirings run in the row direction: a word line, a power supply line, and wiring for gate electrodes of two cross-coupled MOS transistors, and a total of four polysilicon wirings run in the column direction. A total of three aluminum wires, a pair of bit wires and a ground wire, were running on the ground. In one direction, the smaller the number of wires made of the same conductive layer, the easier it is to form the wires, which improves the yield and, in turn, improves the degree of integration. Furthermore, the higher the electrical conductivity of the material used for the word line, bit line pair, and power supply line, the faster access to the memory cell can be expected.

[Problem that the invention attempts to solve]

However, in the conventional structure, four polysilicon interconnects run in the row direction and three aluminum interconnects run in the column direction, which limits the ease of interconnect formation, yield, and integration. was. In addition, because the word lines and power lines are formed of the same conductive layer as the polysilicon wiring for the gate electrode, their resistivity is higher than that of highly conductive materials such as aluminum, which prevents faster access times. Ta.

In view of the problems with the conventional type described above, the purpose of the present invention is to form a layered structure by forming at least the ground line of the word line, power supply line, and ground line with a conductive layer made of a good conductivity material different from the wiring layer for the gate electrode. Based on this concept, the present invention aims to improve the yield by facilitating the formation of wiring layers in static semiconductor memory devices, thereby improving the degree of integration and enabling high-speed operation.

[Means for solving problems]

In order to achieve the above purpose, the present invention:
= A word line, a bit line pair, and a ground line are formed on a semiconductor substrate via an insulating layer, and a static memory cell consisting of a MOS transistor is arranged at each intersection of the word line and the bit line pair. In the semiconductor memory device, the wiring for the gate electrode of the MOS transistor is formed of a first conductive layer formed on the semiconductor substrate via the insulating layer, and the ground line is formed of the first conductive layer. A second conductive layer is formed on the second conductive layer through the insulating layer and has a lower resistance than the first conductive layer, and the bit line is formed on the second conductive layer through the insulating layer. a third conductive layer having a lower resistance than the first conductive layer;
There is provided a semiconductor memory device characterized in that the conductive layer is arranged to extend in a direction perpendicular to the direction in which the second conductive layer extends.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings, while comparing them with conventional examples.

FIG. 1 is an equivalent circuit diagram showing one memory cell of a static random access memory to which the present invention is applied. In Figure 1, for memory selection
Word line connected to the gates of MOS transistors Q ₁ and Q ₂
WL is commonly connected, and the drains (or sources) of these transistors are connected to bit lines BL,
Each BL is connected. MOS transistors that are cross-coupled to form a flip-flop
The drains of Q ₃ and Q ₄ and the source (or drain) of transistor Q ₁ Q ₂ are connected to nodes N ₁ and
Connected at N ₂ . Nodes N ₁ and N ₂ are connected to the power supply line V _CC via load resistors R ₁ and R ₂ , respectively. The sources of transistors Q ₃ and Q ₄ are commonly connected to the ground line GND.

FIG. 2 is a plan view showing the conventional physical structure of the static memory cell shown in FIG. 1, FIG. 3 is a sectional view taken along the line -' in FIG. 2, and FIG. FIG. In FIGS. 2 to 4, a MOS transistor is provided on the surface of the semiconductor substrate 1.
An impurity diffusion layer 2 that becomes the source and drain regions of Q ₁ to _{Q 4} is formed (see FIGS. 3 and 4), and a word layer made of polysilicon is formed on the isolation region 3 on the surface of the semiconductor substrate 1. line WL and power line
V _CC runs parallel to the row direction. The gate electrode wiring G ₃ and G ₄ of the cross-coupled MOS transistors Q ₃ and Q ₄ are connected to the word line WL and the power supply line.
It is a conductive layer made of the same polysilicon as V _CC , and is formed between WL and V _CC on the semiconductor substrate with an insulating layer 4 in between (see FIGS. 2 and 4). Load resistors R ₁ and R ₂ are made of polysilicon doped with a reduced amount of impurity ions and are formed on a portion of the diffusion layer 2 and a portion of the power supply line V _CC with an insulating layer 4 interposed therebetween. The gate electrode G ₄ and one end of the load resistor R ₁ are in contact with the diffusion layer 2 communicating with the drain region of the transistor Q ₃ through the contact window N ₁ . Gate electrode wiring _G3 and load resistance
One end of R ₂ and the diffusion layer 2 communicating with the drain region of the transistor Q ₄ are in contact through a contact window N ₂ . The other ends of the load resistors R ₁ and R ₂ are connected to the power supply line V _CC
is in contact with the contact window _N3 . WL, _G3 ,
A bit line BL and a ground line GND are connected to WL, G _{3 ,} G 4 , G 4 , R ₁ , R ₂ , V _CC via an insulating layer ₄ .
It extends in the direction perpendicular to the direction in which V _CC extends, that is, in the column direction. BL, GND are formed by patterning the aluminum layer. Bit line
BL and the diffusion layer below are in contact with each other through a contact window _N4 , a selection transistor _Q1 is formed at the intersection of BL and WL, and a selection transistor Q1 is formed at the intersection of BL and WL. ₂ is formed,
At the intersection of G ₃ and GND, transistor Q ₃ connects G ₄ and
Transistor _Q4 is formed at the intersection with GND. BL and GND are covered with a phosphosilicate glass layer PSG.

As is clear from FIGS. 2 to 4, in the conventional structure, four wires of the same conductive layer made of polysilicon are formed in the row direction for each memory cell, namely, WL, G ₃ , G ₄ , V _CC exists, and 3 of the same conductive layer made of aluminum in the column direction
Book wiring, ie BL, GND, exists.

Next, an embodiment of the present invention will be described using FIGS. 5 to 7.

5 is a plan view showing the physical structure of the static memory cell shown in FIG. 1 according to an embodiment of the present invention, FIG. 6 is a sectional view taken along the line -' in FIG. It is a sectional view taken along the line -' in the figure. In FIGS. 5 to 7, 1, 2, and 3 are the same semiconductor substrate, impurity diffusion layer, and isolation region as in the conventional drawings, respectively. A polysilicon wiring layer WLP for a word line runs in the row direction on the isolation region 3. The gate electrode wiring G ₃ and G ₄ of the cross-coupled MOS transistors Q ₃ and Q ₄ are insulated on the semiconductor substrate 1 using the same polysilicon first conductive layer as the polysilicon wiring layer WLP, as in the conventional case. It is formed through layer 4. Load resistance R ₁ ,
R ₂ is polysilicon with a reduced amount of impurity ion doping, and an insulating layer 4 is formed on a part of the diffusion layer 2.
is formed through. There are no conventional power lines made of polysilicon. WLP, _G3 ,
A word line is placed on G ₄ , R ₁ , R ₂ via an insulating layer 4.
WL, ground line GND, and power line V _CC are formed parallel to G ₃ and G ₄ . Word line WL is in contact with polysilicon wiring layer WLP. WL, GND, and V _CC are constructed with a second conductive layer made of a highly conductive material such as molybdenum, tungsten, or aluminum. Insulating layer 4 on top of WL, GND and V _CC
Bit line pairs BL and are formed extending in a direction perpendicular to the direction in which WL etc. extend, that is, in the column direction. The bit line pair BL is also constructed of a third conductive layer made of a highly conductive material such as aluminum, as in the conventional case. BL, is covered with PSG as before. contact window
_N1 to _N2 are provided in the same manner as in the conventional case.

As can be seen by comparing the conventional example shown in FIG. 2 and the embodiment of the present invention shown in FIG. In this embodiment, the bit line pair BL,
Only three of them run in the column direction. For this reason,
The interval l ₁ between wiring lines in the column direction is larger in this embodiment than in the conventional example when the dimensions of the memory cells are the same. This means that the formation of bit line pairs is easier than in the prior art, and therefore the manufacturing yield is improved by this embodiment. Furthermore, in this embodiment, if the spacing l ₁ between the wirings in the column direction is made equal to that of the conventional example, the spacing between the bit line pairs will be approximately half that of the conventional example, and the degree of integration will therefore be greatly increased. improves. Also, looking at the row direction, in the conventional example, the polysilicon power supply line V _CC was formed outside the diffusion layer 2 because it acted as a mask when forming the impurity diffusion layer 2 (Figs. 2 and 4). ), in this example, the power supply line V _CC of aluminum or the like is formed with the second conductive layer after the diffusion layer 2 is formed.
It becomes possible to form the power supply line V _CC so as to partially cover the diffusion layer 2 . For this reason, as can be seen from FIGS. 5 and 7, a part of the power line V _CC and a part of the diffusion layer 2 are overlapped with each other so that the power line
V _CC is formed. With this configuration, the interval l ₂ between the word line WL and the power supply line V _CC becomes shorter than in the conventional example, and this also improves the degree of integration.

Furthermore, the power line V _CC , the ground line GND, and the word line WL are not formed using a diffusion layer but are formed of a highly conductive material, so they cannot be formed on the substrate surface to form active elements such as transistors. V _CC , GND, and WL can be formed so as to cover the diffusion layer, and therefore higher integration is possible compared to the case where V _CC , GND, and WL are formed by diffusion layers.

Furthermore, the word line WL was conventionally made of polysilicon, but in this embodiment it is made of a highly conductive material such as aluminum, so the word line WL is made of polysilicon.
The CR time constant associated with WL is smaller than before,
High-speed operation is possible.

Note that in the above embodiment, the word line WL and the ground line
Although GND and power line V _CC are all formed in the second conductive layer, at least the ground line among WL, GND, and V _CC is formed in the second conductive layer, and the remaining wiring is formed in other conductive layers. A laminated structure including the above is also included in the scope of the present invention.

[Effect of idea]

As described above, according to the present invention, at least one of the word line, power supply line, and ground line is formed of a conductive layer made of a highly conductive material different from the wiring layer for the gate electrode to form a laminated structure. The wiring layer of the memory device can be easily formed, improving manufacturing yield, or the degree of integration can be greatly improved, and high-speed operation can be achieved.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram showing one memory cell of a static type random access memory to which the present invention is applied, FIG. 2 is a plan view showing the conventional physical structure of the static type memory cell of FIG. 1, and FIG. 2 is a sectional view taken along the line -' in FIG. 2, FIG. 4 is a sectional view taken along the line -' in FIG. 2, and FIG. Figure 6 is a plan view showing the structure of Figure 5.
7 is a sectional view taken along the line -' in FIG. 5. 1... Semiconductor substrate, 2... Impurity diffusion layer, 3...
...Isolation region, 4...Insulating layer, WL...Word line,
BL, ... Bit line pair, V _CC ... Power supply line, GND
...Grounding wire, _G3 , _G4 ...Wiring for gate electrode.

Claims (1)

[Scope of utility model registration request] A word line, a bit line pair, and a ground line are formed on a semiconductor substrate via an insulating layer, and a static memory cell consisting of a MOS transistor is arranged at each intersection of the word line and the bit line pair. In the semiconductor memory device, the gate electrode wiring of the MOS transistor is formed of a first conductive layer formed on the semiconductor substrate via the insulating layer, and the ground line is formed of the first conductive layer. A second conductive layer is formed on the second conductive layer through the insulating layer and has a lower resistance than the first conductive layer, and the bit line is formed on the second conductive layer through the insulating layer. a third conductive layer having a lower resistance than the first conductive layer;
A semiconductor memory device characterized in that the conductive layer is arranged to extend in a direction perpendicular to the direction in which the second conductive layer extends.