JPH0380353A - Interruption processing method and data channel device - Google Patents

Abstract

PURPOSE:To release the problem of a conventional detecting delay by securing a constitution where the software nips even other interruption requests produced at a CH interruption when a CPU detects an interruption in a certain look-in cycle. CONSTITUTION:When a data channel device CH 101 gives the interruption factors received from the input/output IO layers 1040 - 104n-1 periodically and en bloc to a CPU 100 as the interruption flags, the channel state words CSW corresponding to the IO devices having the interruptions are successively read out. Then the interruption request flags are reset. Thus plural interruptions can be informed with a single interruption given from the CH 101. As a result, the software nips even other interruption requests produced at a CH interruption when the CPU 100 detects an interruption in a certain look-in cycle. As a result, the problem of a conventional detecting delay, etc., can be released.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data channel device (CH) that accommodates a plurality of input/output devices (IO devices) and a central processing unit (CPU) that controls the CH using the Mahbbut IO method. ) is related to an interrupt processing method between

As shown in Figure 1, CHIOI generally has a CPU of 100
After that, for example, the main memory (MM) 10
This device executes data transfer between the MM102-10 devices 104°-104□3 independently of the CPUI OO according to the contents of the CH control word (CCW) prepared on the CPU 2.

If the data transfer ends normally or abnormally, C
HIOI sets the current state as the channel state word (CSW) and generates an interrupt to CPUI 00.

The present invention uses the Matsubuto IO method as a method for the CPU 100 to control CHIOI (that is, it does not use conventional input/output dedicated instructions such as SIO and HIO, but allocates command write registers and status read registers in the address space, and uses general-purpose (This is a well-known technology that has been used in FDP-11 and other devices since around 1970.)

Furthermore, the present invention allows CI-1 to accommodate multiple 10 devices and to multiplex activation requests from the CPU for different devices (i.e., without waiting for data transfer completion reports for previous activations). Reception, CH,! when having the function of executing data transfer regarding each ■0 device in parallel. :CPU
(software).

It is assumed that the channel status word C8W is placed in the CH and is directly read by the interrupt processing program on the CPU that receives the interrupt.

[Conventional technology]

Conventionally, the following methods have been used as this type of interrupt processing method.

Method A: Sequential interrupt method Method B: Multiple interrupt method Method A is a method of waiting for the next interrupt until the currently occurring interrupt is reset.

FIG. 7 shows a sequence diagram of this type of interrupt processing method.

■CH is a subordinate device DV0 to DVn-.

When the data transfer operation for 1 is completed, the channel status word CSW is edited and registered in the interrupt waiting queue (CSW queue). If the final state register TSR into which the channel state word CSW is to be written is being reset, the CH takes out one channel state word CSW from the C8W queue, sets it in the final state register TSR, and generates an interrupt to the CPU. There are two known notification means: one that uses a dedicated signal line, and one that uses a bus signal line that connects the CPU and CH). Even if the channel status word C3W exists in the C3W queue at this point, the next interrupt will not occur until the final status register TSR is released (reset) by the CPU.

On the other hand, the CPU side first detects an interrupt from the CH, and FIG. 7 shows an example of the "periodic look-in method for interrupt flags" (there are two known interrupt detection methods). One is when the CPU hardware detects an interrupt, it forcibly interrupts the currently executing instruction.
This transfers control to the interrupt processing routine, and the other is to set a mask in advance to prevent the forced operation of the hardware as described above, and then the software transfers control from the CH at a convenient time (usually periodically). (This is a look-in method that looks in and detects the request (flag) set at the time of an interrupt.)

■ When the CPU detects an interrupt by look-in, it analyzes the cause of the interrupt by registering the final status register TS in the CH.
Read R. If it is read correctly, the final status register T
Reset SR.

As a result, the interrupt is canceled within the CH.

(2) When the CH detects the termination state register TSR reset, it refers to the C8W queue, and if it is not empty, takes out one channel state word C3W from the C5W queue again and repeats the same process as above.

Method B is to generate the next interrupt without waiting for the currently generated interrupt to be reset. In method B, when an interrupt factor occurs, the CH immediately interrupts the CPU regardless of whether or not an interrupt is currently occurring. In this case,
It is necessary to provide multiple interrupt notification means. In other words, if dedicated signal lines are used, signal lines must be prepared for the number of devices under the CH, and if vectored interrupts are performed using bus signal lines, different interrupt vector values must be used for each device. There must be. Here, a vectored interrupt is defined as ``The start address of the interrupt processing routine is associated with a vector value, and when an interrupt occurs, the hardware uses the vector value as an index to index the table, and software controls the corresponding interrupt routine. It is a well-known technology that is widely used in systems using microprosensors.

[Problem to be solved by the invention]

(1) In method A, when detecting an interrupt from CH by looking in the request flag, C
CH can handle only one interrupt at most per H.
Even if interrupts occur almost simultaneously within the CP
What is processed by U is "look-in period" x "
This will result in a delay of "number of devices". This becomes a problem when interrupt requests occur simultaneously on the same CH with a high frequency, or when the look-in period of the CPU is relatively long.

(2) Also, in method A, the processing order of the generated interrupts is C.
Since the processing order is fixedly determined within H, the CPU cannot arbitrarily select the processing order, resulting in a lack of flexibility.

(3) On the other hand, in method B, the interrupt notification means provided for each CH, that is, the dedicated signal line requires only one vector value via a bus, and it is difficult to employ in a system where this can become a bottleneck.

Recently, most interrupt control units have been implemented as LSIs, and some have restrictions on the number of vector values that can be taken due to the integration problem.

One object of the present invention is to provide an interrupt processing method in which the worst value of detection delay does not become as large as in the past even when a CPU adopts a look-in interrupt detection method, and an interrupt processing method that can be used directly to implement the interrupt processing method. An object of the present invention is to provide a data channel device that uses

Another object of the present invention is to provide an interrupt processing method that allows software to freely determine the processing order for interrupts that occur almost simultaneously, and a data channel device that can be used directly to implement the interrupt processing method. be.

Furthermore, for another purpose, the interrupt notification means described above [Method B]
An object of the present invention is to provide an interrupt processing method that does not require a plurality of interrupt processing methods, and a data channel device that can be used directly to implement the interrupt processing method.

[Means to solve the problem]

To achieve the above object, the interrupt processing method of the present invention accommodates a central processing unit (CPU) and n (>2) input/output (IO) devices, and performs multiple operations of the input/output devices. In a system configured to include a data channel device (CH) to control, the data channel device (CH)
) periodically collects the interrupt factors from the input/output (RO) device as an interrupt request flag and interrupts the central processing unit (CPU) at once.
After detecting an interrupt, the CPU reads the interrupt request flag, sequentially reads channel state words (CSW) corresponding to the input/output (IO) device generating the interrupt, and then resets the interrupt request flag. shall be.

Furthermore, the data channel device of the present invention controls multiple operations of n (>2) input/output (■○) devices connected to and accommodated via a central processing unit (CPU) having an interrupt reception function. a data channel device (CH) that holds a first interrupt flag register (IFR') that holds flag bits for n human output (IO) devices and a temporary copy of the first interrupt flag register; a second interrupt flag register (IFR) that corresponds to the input/output device, and n final status registers (TSR) that hold a channel status word (CSW) indicating the termination status of the input/output device operation provided corresponding to the input/output device. group, the end of the operation of the input/output device is detected, and the final status register (
termination information/flag setting means for setting the channel device word in the TSR) and setting a flag in the corresponding bit of the first interrupt flag register; Checks whether there is a flag bit set in , and if it exists, the first interrupt flag register (
IFR') to the second interrupt flag register (IF
Shifting to R), the present invention is characterized by comprising an interrupt generating means for generating an interrupt to the central processing unit having the interrupt reception function.

[For production]

According to the present invention, multiple interrupts can be notified with one interrupt from CH, so when the CPU detects an interrupt in a certain look-in period, the software can also notify other interrupt requests that were occurring at the time of the CH interrupt. Since it is harvested at regular intervals, the conventional problem of detection delay can be alleviated.

Furthermore, after reaping, the processing order can be determined by the CPU.

Furthermore, the number of interrupts from the channel device to the CPU can also be reduced compared to the conventional system.

Furthermore, in the present invention, since the next interrupt is not generated until the interrupt is reset, only one interrupt notification means such as a vector value or an interrupt signal line is required.

Examples will be described below based on the drawings.

〔Example〕

FIG. 2 is an example of a system configuration to which the present invention is applied.

In Figure 2, 100 is the CPU, 101 is the CH, 10
2 is CPU100. The main memory (memory) device MM, which can be accessed directly from CHIOI, 103 is the CPU, CH, M
A system bus connecting M, 104. ~104. l-I
is an IO device, and 105 is an IO interface bus that connects CH and 10 devices.

Furthermore, the CPU 100 includes a main control unit (MPU) 100-1.
, system bus interface control unit (SBIF) 1
00-2, ROM section 100-3 that holds programs
, an interrupt control unit (
IRC) 100-4, MPUI 00-1~IRC1
It is configured to include a CPU local pulse 100-5 to which 00i is connected.

CHIOI also includes L-MPUIol-1, a local MPU that executes the main functions of CH according to a program, system bus interface control unit 5BIFIOI-2,
Adapter unit ADPI01-3 that interfaces between the 5BIF and CH local buses, ROM that holds programs and various data and is also used as a buffer.
/RAM unit 101-4, IO interface bus control unit 108F1015 that performs time division multiplexing of the IO interface bus with each device (for example, NEC SC3I controller “μPD72111”, etc.)
It consists of:

The interrupt control unit IRC contains an interrupt request register (I
RR), interrupt mask register (IMR), etc., and the adapter part ADP 101-3 includes n final status registers TSRi (i=o, 1, .
. . , n-1), first and second interrupt flag registers IFR', IFR, etc. are included.

The operation of the present invention will be described below with reference to FIGS. 3 to 5.

Explain using.

Processing by firmware of L-MPU in CH: (]) Channel status word C8W, setting of interrupt flag (see Figure 3) L-MPU is connected to peripheral 10 interface bus control unit l0
When a command execution end interrupt for a certain device (referred to as i) is detected from BF, the interrupt processing program reads the status register in the IO interface bus control unit l0BF, analyzes the device number and interrupt cause, and notifies the CPU. power channel state word CS
Edit W. The channel state word CSW holds the state at the end of the input/output operation, the device number, etc. Then, this channel state word C8W is set in the final state register TSRi of the control register corresponding to the device, and bit "1" is set as the interrupt request flag in the corresponding bit position on the first interrupt flag register IFR'. , terminate the interrupt handling program.

The above processing is executed every time an input/output operation with a device is completed.

(21CPU interrupt processing (see Figure 4)) On the other hand,
The L-MPU includes a program that is activated at regular intervals independently of the above-mentioned interrupt processing, and thereby generates an interrupt to the CPU. (The period here is CP
It is more effective if it is shorter than the U (soft) interrupt look-in period. ) That is, when it is activated periodically, it first checks the flag on the first interrupt flag register IFR' and
If 'O', exit without doing anything.

If one or more flags are set, an interrupt factor exists, and the first interrupt flag register IFR" is set to C.
Second interrupt flag register IF serving as a window to the PU
Copy to R and write it to the first interrupt flag register IFR'
is reset and released for setting the next interrupt flag. Then, an interrupt to the CPU is generated. As the means for notifying an interrupt, it is possible to use a signal line dedicated to interrupts or a bus signal line, but either one may be used here.

For example, if a bus signal line is used, the interrupt control unit IRC1 is connected via the adapter unit ADPIOI-3 and the system bus interface control unit 5BIFIOI-2.
The process of writing the vector value to the interrupt request register IRR in 00-4 may be performed.

This access is performed by the system bus 103 and the CPU internal system bus interface control unit 5BIF 100-2.
, reaches the interrupt control unit IRC1004 via the CPU local bus 1005, and interrupts the interrupt control unit IRC1.
In 00-4, the vector (direct) via the system bus is detected and "1" is set in the corresponding bit position in the interrupt request register IRR.The interrupt mask in the interrupt control unit IRC, and the initial setting in the register IMR register. Since a mask is set for that vector by the CPU, the interrupt control unit IRC sends the main control unit MPUl0
(No interrupt occurs for 1-1.

Processing by software in the CPU: Next, interrupt processing by the software in the CPU will be explained with reference to FIG. Here, an example will be explained in which interrupt detection is performed by look-in. However, it is clear that the invention also works with non-look-in methods.

In order to perform interrupt detection by look-in, the CPU sets a mask bit corresponding to CH on the interrupt mask register 51MR in the interrupt control unit IRC so that an interrupt for CH will not be generated from the interrupt control unit IRC at the initial setting stage of the system. “I’ll put a cent on 1゛.

■ When CH interrupt acceptance processing is activated periodically, first the interrupt request register IR in the interrupt control unit IRC is activated.
Read the R register and check whether the CH interrupt flag is ON.

If it is ON, it is determined that there is an interrupt and the process proceeds to the next step.

If it is OFF, it ends.

08 interrupt processing continues with the adapter part ADPI in the CH.
Read the second interrupt flag register IFR of the control registers provided in OI-3.

Note that the second interrupt flag register IFR is allocated in the address space using the Masopd 10 method, so C
The PU can be easily accessed using general purpose load/store instructions. That is, the control register is allocated to a part of the address space, and its address is assigned to the main control unit MP.
When generated from Ul0I-1, it reaches the adapter unit ADPIOI-3 by the system bus interface control unit 5BIF100-2. It is.

■ Next, ° on the second interrupt flag register IFR.
For each device i corresponding to the focus position i where "1" is set, reading the final status register TSRi and registering it in the handover queue to the upper program are repeatedly executed, and all the devices where "1" is set are When the device is finished, the interrupt request flag bit on the interrupt request register IRR in the interrupt control unit IRC is cleared and the second interrupt flag register IFR is reset in this order, and the process ends.

Based on the above, a sequence diagram between CPU and CH is shown in FIG.

Next, some other types B of the present invention will be shown.

In the above embodiments, the case where there is one CPU has been described, but it is clear that a specific one in a multiprocessor configuration may be used.

The internal block configuration of the CHSCPU shown in FIG. 2 is just an example, and any configuration may be used as long as it satisfies the flow shown in FIGS. 3 to 5, that is, as long as it satisfies the gist of the present invention. For example, the 10 devices under CH in FIG. 2 may be of different types, and do not need to be accommodated in the same bus.

In addition, numerous modifications can be made without departing from the effects of the present invention.

[Effects of the Invention] As explained in detail above, according to the present invention, multiple interrupts can be notified with one interrupt from the CH.
When the CPU detects an interrupt in a certain run-in period, the software also reaps other interrupt requests that occurred at the time of the 08 interrupt in that period, so the conventional problem of detection delay can be alleviated.

Furthermore, after reaping, the processing order can be determined by the CPU. Furthermore, the number of interrupts from the channel device to the CPU can also be reduced compared to the conventional system.

Furthermore, in the present invention, since the next interrupt is not generated without waiting for the interrupt reset, only one interrupt notification means such as a hector value or an interrupt signal line is required.

[Brief explanation of drawings]

FIG. 1 is an example of a general configuration of a system including a CH, FIG. 2 is an example of a system configuration to which the present invention is applied, and FIG. Figure 5 is a flowchart of interrupt processing for the CPU by the MPU firm. Figure 6 is an example of a sequence diagram of the interrupt processing method of the present invention. Figure 7 is an example of a sequence diagram of a conventional interrupt processing method. It is. O...Central processing unit, L...Data channel device, 2...Main storage device, 3...System bus, 4o~104□1...■0 device, 0-1...Main Control unit, 0-2.101-2...System bus/ink face control unit, 100-4...Interrupt control unit, 100-5...CPU local bus, 101-1...
・Local MPU. 101-3...adapter section,

Claims (2)

[Claims] (1) It is configured to include a central processing unit (CPU) and a data channel device (CH) that accommodates n (>2) input/output (IO) devices and controls multiple operations of the input/output devices. In the system, the data channel device (CH)
periodically collects the interrupt factors from the input/output (IO) device as an interrupt request flag and interrupts the central processing unit (CPU) all at once.
After detecting an interrupt, U) reads the interrupt request flag, sequentially reads the channel state word (CSW) corresponding to the input/output (IO) device generating the interrupt, and then,
An interrupt processing method comprising resetting the interrupt request flag. (2) Central processing unit (CPU) with interrupt reception function
) is a data channel device (CH) that controls multiple operations of n (>2) input/output (IO) devices connected and accommodated via a bus, a first interrupt flag register (IFR') that holds a flag bit; a second interrupt flag register (IFR) that holds a temporary copy of the first interrupt flag register; and a second interrupt flag register (IFR') that holds a temporary copy of the first interrupt flag register. Holds a channel state word (CSW) indicating the completion status of input/output device operations.
a group of final status registers (TSR); detecting the end of the input/output device operation, setting the channel status word in the final status register (TSR) corresponding to the input/output device, and setting the first interrupt flag; a termination information/flag setting means that sets a flag in a corresponding bit of the register; and a termination information/flag setting means that, when activated at a predetermined cycle, checks whether or not a flag bit that is set on the first interrupt flag register exists; interrupt generation means for transferring the first interrupt flag register (IFR') to the second interrupt flag register (IFR) and generating an interrupt to the central processing unit (CPU) having the interrupt reception function; A data channel device comprising: