JPH0380357B2 - - Google Patents
Info
- Publication number
- JPH0380357B2 JPH0380357B2 JP60163475A JP16347585A JPH0380357B2 JP H0380357 B2 JPH0380357 B2 JP H0380357B2 JP 60163475 A JP60163475 A JP 60163475A JP 16347585 A JP16347585 A JP 16347585A JP H0380357 B2 JPH0380357 B2 JP H0380357B2
- Authority
- JP
- Japan
- Prior art keywords
- pad
- chip carrier
- length
- electrode
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【発明の詳細な説明】
〔概要〕
チツプキヤリアを印刷配線基板に実装するにあ
たり、チツプキヤリアの電極パツドの長さと、印
刷配線基板の基板パツドの長さの比率を所定に設
定し、半田付けの信頼度を向上させる。[Detailed Description of the Invention] [Summary] When mounting a chip carrier on a printed wiring board, the ratio of the length of the electrode pad of the chip carrier to the length of the board pad of the printed wiring board is set to a predetermined value, and the reliability of soldering is determined. improve.
本発明はチツプキヤリアの実装方法の改良に関
する。
The present invention relates to an improvement in a chip carrier mounting method.
電子機器、通信機器等においては、LSI、IC等
の半導体チツプを信号、電源あるいはアース等の
電極パターンが形成された角板状のセラミツク基
台よりなるチツプキヤリアに搭載密封し、このよ
うなチツプキヤリアを基板に多数実装した装置が
広く使用されている。 In electronic equipment, communication equipment, etc., semiconductor chips such as LSIs and ICs are mounted and sealed on chip carriers made of square plate-shaped ceramic bases on which electrode patterns for signals, power, or ground are formed. Devices mounted in large numbers on a board are widely used.
チツプキヤリアを印刷配線基板に実装する従来
の一般的の方法は、第３図の斜視図に示すよう
に、チツプキヤリア１をサブセラミツク基板７を
介して印刷配線基板６に実装している。 A conventional and common method for mounting a chip carrier on a printed wiring board is to mount the chip carrier 1 on a printed wiring board 6 via a sub-ceramic substrate 7, as shown in the perspective view of FIG.
即ち、サブセラミツク基板７の上面には、チツ
プキヤリア１の裏面に設けた電極パツドに対応し
て、基板パツド１０を並設し、それぞれの基板パ
ツド１０は、サブセラミツク基板７の側面に並設
したリード端子８に接続してある。対応する電極
パツドと基板パツド１０とを半田付けすることに
より、チツプキヤリア１をサブセラミツク基板７
に搭載し、その後それぞれのリード端子８を、対
応する印刷配線基板６のスルーホール９に挿着半
田付けしている。 That is, on the upper surface of the sub-ceramic substrate 7, substrate pads 10 are arranged in parallel, corresponding to the electrode pads provided on the back surface of the chip carrier 1, and each substrate pad 10 is arranged in parallel on the side surface of the sub-ceramic substrate 7. It is connected to lead terminal 8. By soldering the corresponding electrode pads and substrate pads 10, the chip carrier 1 is attached to the sub-ceramic substrate 7.
After that, each lead terminal 8 is inserted and soldered into the through hole 9 of the corresponding printed wiring board 6.
チツプキヤリア１を直接印刷配線基板６に実装
すると、セラミツク基台と印刷配線基板（例えば
ガラスエポキシ樹脂等よりなる印刷回路用銅張積
層板）との熱膨張係数の差に起因して、半田付け
部分に亀裂が発生する恐れがある。このことを避
けるために上述のように、サブセラミツク基板７
を介して印刷配線基板６に実装している。 When the chip carrier 1 is directly mounted on the printed circuit board 6, the soldered portion may be damaged due to the difference in thermal expansion coefficient between the ceramic base and the printed circuit board (for example, a copper-clad laminate for printed circuits made of glass epoxy resin, etc.). There is a risk that cracks may occur. In order to avoid this, as mentioned above, the sub-ceramic substrate 7
It is mounted on the printed wiring board 6 via.
しかし、印刷配線基板に部品の高密度搭載化、
小形化に伴い、チツプキヤリア１を直接、印刷配
線基板６に実装することが要求されている。 However, with the high density mounting of components on printed wiring boards,
With miniaturization, it is required to directly mount the chip carrier 1 on the printed wiring board 6.
チツプキヤリアを印刷配線基板に直接に実装す
る従来方法を、第４図の斜視図、及び第５図の要
部断面図を参照して説明する。
A conventional method for directly mounting a chip carrier on a printed wiring board will be described with reference to a perspective view in FIG. 4 and a cross-sectional view of a main part in FIG.
第４図及び第５図において、角板状のセラミツ
ク基台よりなるチツプキヤリア１は、上面に
LSI、IC等の半導体チツプ２が埋設される角形の
凹部が設けられ、凹部の上方には凹部よりも平面
視が大きい角孔が設けられている。 In FIGS. 4 and 5, the chip carrier 1, which is made of a square plate-shaped ceramic base, has a top surface.
A rectangular recess is provided in which a semiconductor chip 2 such as an LSI or an IC is buried, and a square hole that is larger in plan view than the recess is provided above the recess.
角孔の上周縁を含む面で、チツプキヤリア１の
底面に並行する境界面には、凹部のそれぞれの辺
に直交し、チツプキヤリア１の側壁に並設された
後述する端子部４にそれぞれ通じる所望数の、タ
ングステン等をメタライズし、さらに金メツキし
てなる電極パターン３が形成されている。この電
極パターン３は、半導体チツプ２のそれぞれの電
極に、例えばワイヤボンデングされて接続されて
いる。 The boundary surface that includes the upper peripheral edge of the square hole and is parallel to the bottom surface of the chip carrier 1 has a desired number of terminals perpendicular to each side of the recess and connected to the terminal portions 4, which will be described later, arranged in parallel on the side wall of the chip carrier 1. An electrode pattern 3 is formed by metallizing tungsten or the like and plating it with gold. This electrode pattern 3 is connected to each electrode of the semiconductor chip 2 by, for example, wire bonding.
チツプキヤリア１の垂直のそれぞれの側壁に
は、側壁面に垂直方向の深さが一定で、ほぼ半円
柱形に凹んでなるリードレス形の端子部４が並列
して設けられ、それぞれの端子部４の凹面には、
タングステン等をメタライズし、さらに金メツキ
し電極膜を形成して電極パターン３と電気的に接
続している。 On each vertical side wall of the chip carrier 1, leadless terminal portions 4 having a constant depth in the vertical direction on the side wall surface and recessed in an approximately semi-cylindrical shape are provided in parallel. On the concave surface of
It is electrically connected to the electrode pattern 3 by metallizing tungsten or the like and then plating with gold to form an electrode film.
また、チツプキヤリア１の裏面には、それぞれ
の端子部４の凹面に連結した角片状の電極パツド
５が形成されている。 Further, on the back surface of the chip carrier 1, square-shaped electrode pads 5 connected to the concave surfaces of the respective terminal portions 4 are formed.
一方、印刷配線基板６の上面には、チツプキヤ
リア１の電極パツド５に対応して、基板パツド１
０と、基板パツド１０に接続された導体パターン
１１が形成されている。 On the other hand, on the upper surface of the printed wiring board 6, there are board pads 1 corresponding to the electrode pads 5 of the chip carrier 1.
0 and a conductor pattern 11 connected to the substrate pad 10 are formed.
上述のようなチツプキヤリア１を、印刷配線基
板６に実装するには、まず半田が付着しては困る
導体パターン１１上の全面に半田レジスト膜を塗
布し、その後、印刷配線基板６の基板パツド１０
の上面に半田ペーストを、例えばスクリーン印刷
などして塗布したり、或いは半田プリフオームを
間に入れたりした後に、基板パツド１０に電極パ
ツド５を位置合わせして、チツプキヤリア１を載
置し、例えば赤外線加熱等して、半田層１２を形
成して接着している。 In order to mount the chip carrier 1 as described above on the printed wiring board 6, first, a solder resist film is applied to the entire surface of the conductor pattern 11 where solder should not adhere, and then the board pad 10 of the printed wiring board 6 is coated with a solder resist film.
After applying solder paste to the upper surface by, for example, screen printing or inserting a solder preform, the electrode pads 5 are aligned with the substrate pads 10, the chip carrier 1 is mounted, and the A solder layer 12 is formed and bonded by heating or the like.
この接着時に、基板パツド１０と電極パツド５
との関係寸法を所望に規制すると、半田層１２の
溶融状態の半田の表面張力で、電極パツド５と基
板パツド１０とが互いに近寄る方向に引つ張られ
て、チツプキヤリア１の実装位置の位置合わせが
自動的に行われる。 At the time of this bonding, the substrate pad 10 and the electrode pad 5
When the related dimensions are regulated as desired, the surface tension of the molten solder in the solder layer 12 pulls the electrode pad 5 and the board pad 10 toward each other, thereby aligning the mounting position of the chip carrier 1. is done automatically.
しかし基板パツド１０の長さが所定値より大き
くなると、このような作用が弱くなり、チツプキ
ヤリア１の位置がずれて、所定のパツドでない隣
接したパツドに接続される等、接続不良となる恐
れがある。 However, when the length of the board pad 10 becomes larger than a predetermined value, this effect becomes weaker, and there is a risk that the position of the chip carrier 1 will be shifted and a connection failure may occur, such as being connected to an adjacent pad other than the predetermined pad. .
実験より得られた、このような位置ずれ発生の
特性図を第６図ａに示す。 A characteristic diagram of the occurrence of such positional deviation obtained from an experiment is shown in FIG. 6a.
第６図ａは縦軸に位置ずれ発生頻度を、横軸に
電極パツド５（長さLa）と基板パツド１０（長
さLb）の長さの比率（Lb／La）をとつている。 In FIG. 6a, the vertical axis represents the frequency of misalignment, and the horizontal axis represents the length ratio (Lb/La) of the electrode pad 5 (length La) to the substrate pad 10 (length Lb).
この特性は右上がりに上昇する曲線Ａで示さ
れ、（Lb／La）が1.1〜1.3の間では殆ど位置ずれ
不良が発生しなく、（Lb／La）が1.7を越えると
急激に不良が発生することを示している。 This characteristic is shown by curve A that rises upward to the right. When (Lb/La) is between 1.1 and 1.3, positional deviation defects hardly occur, and when (Lb/La) exceeds 1.7, defects suddenly occur. It shows that.
したがつて、基板パツド１０の長さLbを電極
パツド５の長さLa（例えば１mm）よりも所望長
（例えば0.3mm）だけ長くして、（Lb／La）を1.3前
後にしている。 Therefore, the length Lb of the substrate pad 10 is made longer than the length La (eg 1 mm) of the electrode pad 5 by a desired length (eg 0.3 mm), so that (Lb/La) is around 1.3.
なお、基板パツド１０の幅は電極パツド５の幅
（例えば0.8mm）に等しいか、わずかに大きい。 Note that the width of the substrate pad 10 is equal to or slightly larger than the width of the electrode pad 5 (for example, 0.8 mm).
しかしながら上記の如く印刷配線基板６に直接
チツプキヤリア１を実装した場合には、印刷配線
基板６とチツプキヤリア１のセラミツク基台の熱
膨張係数の差が大きいことに起因して、実装時の
加熱、稼動時の発熱等により、半田層１２に応力
が付加される。この応力は、チツプキヤリア１の
周辺の中心より離れるに従い大きく、チツプキヤ
リア１の隅近傍の電極パツド５の半田層１２に亀
裂が発生する恐れがある。
However, when the chip carrier 1 is mounted directly on the printed wiring board 6 as described above, due to the large difference in thermal expansion coefficient between the printed wiring board 6 and the ceramic base of the chip carrier 1, heating during mounting and operation Stress is applied to the solder layer 12 due to heat generated during the process. This stress increases as the distance from the center of the periphery of the chip carrier 1 increases, and there is a risk that cracks may occur in the solder layer 12 of the electrode pad 5 near the corners of the chip carrier 1.
したがつて、従来の実装手段で、形状の大きい
チツプキヤリア１を、直接印刷配線基板６に実装
すると、半田付けの信頼度が低下するという問題
点があつた。 Therefore, when the large-sized chip carrier 1 is directly mounted on the printed wiring board 6 using conventional mounting means, there is a problem in that the reliability of soldering decreases.
上記従来の問題点を解決するため本発明は、チ
ツプキヤリア１の裏面に並設した電極パツド５の
長さを一定に形成して、隅部に設けた電極パツド
５に対応する基板パツド１０Ｎの長さは、電極パ
ツド５の長さの1.5倍乃至1.7倍の範囲に形成し、
周辺の中心に近づくにつれて、基板パツドの長さ
は、その倍率を小さくし、それぞれの周辺の中心
部の電極パツド５に対応する基板パツド１０Ａの
長さは、1.1倍乃至1.3倍の範囲に形成して、半田
付け実装するようにしたものである。
In order to solve the above-mentioned conventional problems, the present invention has a structure in which the lengths of the electrode pads 5 arranged in parallel on the back surface of the chip carrier 1 are constant, and the lengths of the substrate pads 10N corresponding to the electrode pads 5 provided at the corners are fixed. The length is formed in a range of 1.5 to 1.7 times the length of the electrode pad 5,
The length of the substrate pad decreases its magnification as it approaches the center of the periphery, and the length of the substrate pad 10A corresponding to the electrode pad 5 at the center of each periphery is formed in the range of 1.1 to 1.3 times. Then, it was mounted by soldering.
熱歪に起因し半田層１２に亀裂が発生する不良
発生頻度は、実験より第６図ｂのような特性図が
得られている。
As for the frequency of occurrence of defects in which cracks occur in the solder layer 12 due to thermal strain, a characteristic diagram as shown in FIG. 6b has been obtained through experiments.
第６図ｂは垂直のＺ軸に熱歪による不良発生頻
度を、Ｘ軸に半田層１２の厚さｈを、Ｙ軸に
（Lb／La）をとつてある。 In FIG. 6b, the vertical Z-axis shows the frequency of defects caused by thermal strain, the X-axis shows the thickness h of the solder layer 12, and the Y-axis shows (Lb/La).
不良頻度と（Lb／La）との関係は曲線Ｂで示
すように、（Lb／La）が1.3より小さくなると急
激に上昇する。また半田層１２の厚さｈと、不良
頻度との関係は曲線Ｃで示すように、ｈが70μm
より小さくなると急激に上昇する。 As shown by curve B, the relationship between failure frequency and (Lb/La) sharply increases when (Lb/La) becomes smaller than 1.3. In addition, the relationship between the thickness h of the solder layer 12 and the failure frequency is as shown by curve C, when h is 70 μm.
When it gets smaller, it increases rapidly.
第６図ａ，ｂの不良発生頻度特性図より、推考
されるように、上記本発明の手段によれば、熱歪
による応力が最大である隅部に設けた電極パツド
５に対応する基板パツド１０Ｎの長さを、電極パ
ツド５の長さの1.5倍乃至1.7倍であるので、半田
層１２に亀裂の発生する恐れが少ない。 As can be inferred from the failure occurrence frequency characteristic diagrams shown in FIGS. Since the length of 10N is 1.5 to 1.7 times the length of the electrode pad 5, there is little risk of cracks occurring in the solder layer 12.
また、チツプキヤリア１のそれぞれの辺の中心
部の電極パツド５に対応する基板パツド１０Ａの
長さは、1.1倍乃至1.3倍の範囲に形成してあるの
で、この部分の溶融状態の半田により、チツプキ
ヤリア１の位置合わせが行われ、印刷配線基板６
の所定の位置にチツプキヤリア１が載置される。
したがつて、隅部に設けた電極パツド５と基板パ
ツド１０Ｎとの間にも位置ずれが発生する恐れが
少ない。 In addition, since the length of the substrate pad 10A corresponding to the electrode pad 5 at the center of each side of the chip carrier 1 is formed in the range of 1.1 to 1.3 times, the molten solder in this part can cause the chip carrier to 1 alignment is performed, and the printed wiring board 6
The chip carrier 1 is placed at a predetermined position.
Therefore, there is little possibility that misalignment will occur between the electrode pad 5 provided at the corner and the substrate pad 10N.
即ち、形状の大きいチツプキヤリア１を印刷配
線基板６に実装した場合でも、位置ずれが少な
く、且つ熱歪に起因する亀裂が半田接着部分に発
生する恐れが少なく、信頼度が向上する。 That is, even when the chip carrier 1 having a large shape is mounted on the printed wiring board 6, there is little misalignment and there is little fear that cracks due to thermal strain will occur in the solder bonded portion, improving reliability.
〔実施例〕
以下図示実施例により、本発明を具体的に説明
する。なお、全図を通じて同一符号は同一対象物
を示す。[Examples] The present invention will be specifically explained below with reference to illustrated examples. Note that the same reference numerals indicate the same objects throughout the figures.
第１図は本発明の１実施例の平面図であり、第
２図ａは隅部、即ち第１図に示す鎖線X1−X1部
分の断面図、ｂは辺の中心部、即ち第１図に示す
鎖線X2−X2部分の断面図である。第１図及び第
２図において、印刷配線基板６の上面には、チツ
プキヤリア１の電極パツド５に対応して、基板パ
ツドが角形のそれぞれの４辺に並列して形成さ
れ、それぞれの基板パツドより四方に放射状に導
体パターン１１が形成されている。 FIG . 1 is a plan view of one embodiment of the present invention, FIG . FIG. 2 is a sectional view taken along the chain line X 2 -X 2 shown in FIG. 1 and 2, on the upper surface of the printed wiring board 6, board pads are formed in parallel on each of the four sides of the rectangular shape, corresponding to the electrode pads 5 of the chip carrier 1. Conductor patterns 11 are formed radially in all directions.
この基板パツドの内側の側辺が形成する角形枠
の大きさは、チツプキヤリア１の裏面に設けた基
板パツドの内側の側辺が形成する角形枠の大きさ
に等しくしてある。 The size of the rectangular frame formed by the inner sides of this substrate pad is made equal to the size of the rectangular frame formed by the inner sides of the substrate pad provided on the back surface of the chip carrier 1.
チツプキヤリア１の隅部に設けた電極パツド５
に対応する印刷配線基板６の、基板パツド１０Ｎ
の長さLb1は第２図ａに示すように、電極パツド
５の長さLaの1.5倍乃至1.7倍の範囲に形成してあ
る。 Electrode pad 5 provided at the corner of chip carrier 1
The board pad 10N of the printed wiring board 6 corresponding to
As shown in FIG. 2a, the length Lb1 is set in the range of 1.5 to 1.7 times the length La of the electrode pad 5.
そして、周辺の中心に近づくにつれて、基板パ
ツドの長さは、その倍率を小さく、それぞれの周
辺の中心部の電極パツド５に対応する基板パツド
１０Ａの長さはLb2は、第２図ｂに示すように、
電極パツド５の長さLaの1.1倍乃至1.3倍の範囲に
形成してある。 The length of the substrate pad decreases as it approaches the center of the periphery, and the length of the substrate pad 10A corresponding to the electrode pad 5 at the center of each periphery is Lb 2 as shown in FIG. 2b. As shown,
It is formed in a range of 1.1 to 1.3 times the length La of the electrode pad 5.
なお、このそれぞれの基板パツドの長さを上述
のように変えて形成せず、十分に長く形成し、導
体パターン１１上の全面に半田レジスト膜１５を
塗布する際に、第１図、第２図のように、内枠の
それぞれの辺を点線で示すように内側に凸のピラ
ミツト形に塗布して、それぞれの基板パツドの露
出長さを、上述の寸法にしても良い。 Note that when the lengths of the respective substrate pads are not changed as described above, but are formed sufficiently long, and the solder resist film 15 is applied to the entire surface of the conductor pattern 11, the lengths shown in FIGS. As shown in the figure, each side of the inner frame may be coated in an inwardly convex pyramid shape as indicated by dotted lines, and the exposed length of each substrate pad may be set to the above-mentioned dimensions.
その後、印刷配線基板６の基板パツドの上面に
半田ペーストを、例えばスクリーン印刷などして
塗布したり、或いは半田プリフオームを間に入れ
たりした後に、基板パツド１０に電極パツド５を
位置合わせして、チツプキヤリア１を載置し、例
えば赤外線加熱等して、半田層１２を形成してチ
ツプキヤリア１を印刷配線基板６に実装してい
る。 After that, after applying solder paste to the upper surface of the board pad of the printed wiring board 6 by, for example, screen printing, or inserting a solder preform in between, the electrode pad 5 is aligned with the board pad 10, The chip carrier 1 is mounted on the printed wiring board 6, and a solder layer 12 is formed by, for example, infrared heating.
上述のようにして実装されたチツプキヤリア１
は、各辺の中心近傍の基板パツドは勿論のこと、
熱歪による応力が最大である隅部に設けた電極パ
ツド５に対応する基板パツド１０Ｎ部分の半田層
１２に、亀裂が発生することが殆ど無くて、亀裂
発生頻度が従来の15％以下となつた。 Chip carrier 1 implemented as described above
Of course, the board pad near the center of each side,
Almost no cracks occur in the solder layer 12 in the part of the board pad 10N corresponding to the electrode pad 5 provided at the corner where stress due to thermal strain is maximum, and the frequency of crack occurrence is 15% or less compared to the conventional method. Ta.
また、中心部の電極パツド５に対応する基板パ
ツド１０Ａの長さは、1.1倍乃至1.3倍の範囲に形
成してあるので、この部分の溶融状態の半田によ
り、チツプキヤリア１の位置合わせが行われる。
したがつて、他の電極パツドと対応する基板パツ
ド間に、位置ずれが発生することがない。 Furthermore, since the length of the substrate pad 10A corresponding to the electrode pad 5 at the center is formed in a range of 1.1 to 1.3 times, the positioning of the chip carrier 1 is performed by the molten solder in this part. .
Therefore, no misalignment occurs between the substrate pads corresponding to other electrode pads.
以上説明したように本発明は、チツプキヤリア
の電極パツドの長さと印刷配線基板の基板パツド
の長さの比率を所定に設定したことにより、形状
の大きいチツプキヤリアに適用して、チツプキヤ
リアと印刷配線基板の熱膨張係数の差に起因する
熱歪により、接着部の半田に亀裂が殆ど発生しな
いという優れた効果を有する。
As explained above, the present invention can be applied to large-sized chip carriers by setting the ratio of the length of the electrode pad of the chip carrier to the length of the board pad of the printed wiring board to a predetermined value. It has an excellent effect in that almost no cracks occur in the solder at the bonded portion due to thermal strain caused by the difference in thermal expansion coefficients.
さらにまた、チツプキヤリアの電極パツドと印
刷配線基板の基板パツド間の、位置ずれがないと
いう効果を奏する。 Furthermore, there is an effect that there is no misalignment between the electrode pads of the chip carrier and the board pads of the printed wiring board.
第１図は本発明の１実施例の平面図、第２図ａ
は第１図に示す鎖線X1−X1部分の断面図、ｂは
第１図の鎖線X2−X2部分の断面図、第３図は従
来の実装手段を示す斜視図、第４図は従来の他の
実装手段を示す斜視図、第５図は第４図に示す従
来例の要部断面図、第６図は不良発生特性図で、
ａは位置ずれ発生頻度図、ｂは熱歪による不良発
生頻度図である。
図において、１はチツプキヤリア、２は半導体
チツプ、３は電極パターン、４は端子部、５は電
極パツド、６は印刷配線基板、１０，１０Ａ，１
０Ｎは基板パツド、１１は導体パターン、１２は
半田層、１５は半田レジスト膜を示す。
Fig. 1 is a plan view of one embodiment of the present invention, Fig. 2a
is a sectional view taken along the chain line X 1 -X 1 shown in FIG. 1, b is a sectional view taken along the chain line X 2 - X 2 shown in FIG. 1, FIG. 3 is a perspective view showing the conventional mounting means, and FIG. is a perspective view showing another conventional mounting means, FIG. 5 is a sectional view of the main part of the conventional example shown in FIG. 4, and FIG. 6 is a failure occurrence characteristic diagram.
A is a diagram of the frequency of misalignment occurrence, and b is a diagram of the frequency of defects caused by thermal strain. In the figure, 1 is a chip carrier, 2 is a semiconductor chip, 3 is an electrode pattern, 4 is a terminal part, 5 is an electrode pad, 6 is a printed wiring board, 10, 10A, 1
0N is a substrate pad, 11 is a conductor pattern, 12 is a solder layer, and 15 is a solder resist film.
Claims (1)
の裏面の周辺に並設した電極パツド５のそれぞれ
に対応した基板パツドを設け、該電極パツド５と
該基板パツドを半田付けして該チツプキヤリア１
を実装するにあたり、 該電極パツド５の長さを一定に形成して、隅部
に設けた該電極パツド５に対応する該基板パツド
１０Ｎの長さは、該電極パツド５の長さの1.5倍
乃至1.7倍の範囲に形成し、 周辺の中心に近づくにつれて、該基板パツドの
長さは、その倍率を小さくし、 それぞれの周辺の中心部の該電極パツド５に対
応する該基板パツド１０Ａの長さは、1.1倍乃至
1.3倍の範囲に形成して、半田付けすることを特
徴とするチツプキヤリアの実装方法。[Claims] 1 A chip carrier 1 is provided on the surface of the printed wiring board 6.
A substrate pad corresponding to each of the electrode pads 5 arranged in parallel is provided around the back surface of the chip carrier 1, and the electrode pads 5 and the substrate pad are soldered to each other.
When mounting, the electrode pads 5 are formed to have a constant length, and the length of the substrate pad 10N corresponding to the electrode pad 5 provided at the corner is 1.5 times the length of the electrode pad 5. The length of the substrate pad 10A corresponding to the electrode pad 5 at the center of each periphery decreases as it approaches the center of the periphery. It is 1.1 times to
A chip carrier mounting method characterized by forming a 1.3 times larger area and soldering it.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16347585A JPS6224691A (en) | 1985-07-24 | 1985-07-24 | Packaging of chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16347585A JPS6224691A (en) | 1985-07-24 | 1985-07-24 | Packaging of chip carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6224691A JPS6224691A (en) | 1987-02-02 |
| JPH0380357B2 true JPH0380357B2 (en) | 1991-12-24 |
Family
ID=15774577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16347585A Granted JPS6224691A (en) | 1985-07-24 | 1985-07-24 | Packaging of chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6224691A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006147723A (en) * | 2004-11-17 | 2006-06-08 | Sharp Corp | Electric circuit board for semiconductor elements |
-
1985
- 1985-07-24 JP JP16347585A patent/JPS6224691A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6224691A (en) | 1987-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5367435A (en) | Electronic package structure and method of making same | |
| KR0157284B1 (en) | Printed circuit board of solder ball take-on groove furnished and this use of package ball grid array | |
| US5278724A (en) | Electronic package and method of making same | |
| US5561328A (en) | Photo-definable template for semiconductor chip alignment | |
| US7019221B1 (en) | Printed wiring board | |
| JPH0767002B2 (en) | Circuit package structure | |
| KR20020065045A (en) | Semiconductor chip package comprising enhanced pads | |
| US6410861B1 (en) | Low profile interconnect structure | |
| JP3016910B2 (en) | Semiconductor module structure | |
| JPH05259372A (en) | Hibrid ic | |
| JPS6224691A (en) | Packaging of chip carrier | |
| JP2905299B2 (en) | Heat dissipation structure and heat sink mounting method | |
| JPH0438522Y2 (en) | ||
| JP2901955B1 (en) | Circuit board, board mounting method and circuit assembly | |
| EP0343379A2 (en) | Thin film package for mixed bonding of a chip | |
| KR19990002341A (en) | Printed circuit board for mixing heterogeneous chip parts and manufacturing method | |
| JPH0645763A (en) | Printed wiring board | |
| JPH0810192Y2 (en) | Semiconductor mounting structure | |
| JPS634690A (en) | Thick film hybrid integrated circuit substrate | |
| US20050094383A1 (en) | Substrate for use in forming electronic package | |
| JPH02114595A (en) | Mounting of chip component | |
| JP2003068920A (en) | Wiring board | |
| JP3170033B2 (en) | Electronic circuit device | |
| JPH06318666A (en) | Ceramic package | |
| JP2004327912A (en) | Semiconductor package and semiconductor device |