JPH038043A - Device connecting system - Google Patents

Abstract

PURPOSE:To connect a lot of devices to a single host device without limiting the number of the devices to be connected by a low-ordr interface by providing a means to select the low-order interface in correspondence to a device number from the host device. CONSTITUTION:Plural low-order interfaces 14-1 and 14-2 are provided to a host device 10 and an (N-1)-number of devices 12 are connected for each low- order interface. Then, a selecting means 16 is provided to select and connect one of the low-order interfaces in correspondence to the device number form the device 10. Accordingly, through the means 16, the number of the devices to be connected can be increased without being limited by the low-order interface. For example, since an SCSI interface can connect the 8 devices at a maximum, when the two SCSI interfaces are selected and connected to the device 10, the 7 devices for each SCSI interface, totally, the 14 devices can be connected. Thus, without limiting the number of the devices to be connected by the low-order interface, a lot of the devices can be connected to the single host device.

Description

[Detailed Description of the Invention] [Summary] Regarding a device connection method that connects multiple devices to a host device using an SC8I interface, the present invention aims to enable connection of a large number of devices without being restricted by the number of connected devices due to the interface. The purpose is to provide multiple lower-level interfaces to a single higher-level device, connect one device less than the maximum number of connections N (N-1) to each interface, and connect devices according to the device number from the higher-level device. The configuration is such that the corresponding interface is selected and connected by the selection means.

[Industrial Field of Application] The present invention relates to a device connection method for connecting a plurality of devices to a host device using a SCSI interface or the like.

SCSI (SmalCampul) is an interface for connecting disk-based devices to a personal computer to configure an appropriate system.
cr Sysjcm In+etlacc) has been put into practical use.

5C8I, commonly known as Scashi, is a maximum of 8 for the SC8I bus.
Of the eight devices, the device that issues the command is defined as the initiator, and the device that receives and executes the command is defined as the target, and the initiator and target may be fixedly determined. However, it may also serve as an initiator or a target during processing. As a result, the 5C81 bus becomes a bidirectional bus in which any device connected to it can stand on an equal footing, and is characterized by high flexibility in system configuration.

By the way, in recent years, the number of devices connected to a host device in a single system has tended to increase due to improvements in the processing performance of host devices and increases in file capacity. In this case, the number of devices connected to the host device is restricted, and it is desirable to be able to increase the number of devices connected without impairing the interface function.

[Prior Art] FIG. 6 is an explanatory diagram of a conventional method using an SC8I interface.

In FIG. 6, 10 is a CPU as a host device, and CPU10 is a director 1 as a host adapter.
8 to the SC8I interface 14.

The SC8I interface 14 can connect up to eight devices, and in this case, seven devices other than the CPU10, such as a magnetic disk device and a magneto-optical disk device, are connected.

Here, since CPUl0 is a device that issues instructions, SC
From the perspective of the 8I interface 14, the director 18 is defined as an initiator, and also the devices 12-1 to 12-7.
is defined as a target because it executes operations such as read and write upon receiving instructions from CPU10, and is defined as an embedded type because it integrates the drive circuit. Also, system-wise, CPU 10 issues instructions to device 12-1.
~12-7 only execute instructions, so the initiator and target are placed in a fixed relationship.

The director 18 includes a driver/receiver 20 that exchanges commands, data, etc. with the CPU10, a channel interface controller 22 that controls the interface with the host channel, and a data transfer buffer 24.5C8I that temporarily stores transfer data. An interface control circuit 26 is provided to control the devices 12-1 to 1 based on commands from the CPU 10 under the control of the MPU 28.
Controls 2-7 are performed, and various information necessary for this control is stored in the control memory 30.

[Problems to be Solved by the Invention] However, in a device connection method in which multiple devices are connected to a host device using such an SCSR interface, the 5C8I interface can only connect up to 8 devices. Because connection is not possible, only a maximum of 7 devices can be connected to the host device, and S
The adoption of the CSI interface limits the number of devices that can be connected, making it impossible to expand the system scale.

The present invention has been made in view of these conventional problems, and it is an object of the present invention to provide a device connection method that allows a large number of devices to be connected to a single host device without being limited by the number of devices connected by the lower-level interface. purpose.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

First, the present invention connects a plurality of devices 1 to a host device 10 via a lower-order interface for which the maximum number N of devices to be connected is determined.
This applies to device connection methods that connect 2 devices.

In the present invention, regarding such a device connection method,
Multiple lower level interfaces 14-1 for the higher level device 10
．． 14-2 and each lower interface 14-1.1
Selection of connecting (N-1) devices 12 to each 4-2 and selecting and connecting one of the plurality of lower-level interfaces 14-1 and 14-2 according to the device number from the higher-level device 10. A means 16 is provided.

Here, as the lower interface 14-1, 14-2, for example, an SC8I interface is used, which has a maximum number of connections of eight devices.

[Operation] In the device connection method of the present invention having such a configuration, even if the number of devices connected to a lower-level interface is limited, a plurality of lower-level interfaces can be connected to a higher-level device through the selection means. Since the corresponding lower interface is selectively connected based on the device number included in the command from the higher-level device, the number of connected devices can be increased without being restricted by the lower-level interface.

For example, the SC3I interface can connect up to 8 devices, so if you selectively connect two SC3I interfaces to a host device, you can connect 7 devices to each SCSI interface, for a total of 14 devices. .

Embodiment FIG. 2 is a block diagram showing an embodiment of the present invention.

In FIG. 2, reference numeral 10 denotes a CPU as a host device, and in this embodiment, 5C8I interfaces 14-1, .
14-2 is connected.

SC3I interface 14-1.14-2 has a total of 8
1 device can be connected, and since one of them becomes the director 18, the remaining 7 devices can be connected to the device devices 12-1 to 12-1 for the 5C8I interface 14-1.
7 and also connect as SC3I interface 14-2
are connected as devices 12-8 to 12-14. Here, the devices 12-1 to 12-14 are composed of magnetic disk devices, optical disk devices, etc., and in this embodiment, for example, 14 optical disk devices are connected.

The director 18 is provided with a driver/receiver 20 that exchanges commands and data with the CPU 10, and a channel interface controller 22 that controls transmission with the host 10 following the driver/receiver 20.

Following the channel interface controller 22 is C.
A data transfer buffer 24 is provided to temporarily store data transferred to and from the PUI (R: device).

An SC8I interface control circuit 26-1.26-2 is provided for each of the two SC8I interfaces 14-1.14-2 provided as lower-order interfaces for connecting the further devices 12-1 to 12-14. This SC3I interface control circuit 26-1, 26-2 and the data transfer buffer 24 side are connected via a changeover switch 16 as a selection means, and the 5C
Either one of the SI interface control circuits 26-1 and 26-2 is connected to the data transfer buffer 24 side, that is, the CPU
Selectively connected to the l0 side.

The MPU 28 performs overall control of the director 18, and has two SC3I interface control circuits 26-1.
．． Changeover switch 16 newly installed with 26-2
It has the function to control.

The control function of this changeover switch 16 is performed by the devices 12 connected to the SC3I interfaces 14-1 to 14-2.
-1 to 12-14, set device numbers in advance,
The MPU 28 of the director 18, whose device number is determined upon startup from the CPU10, determines the device number and sends the 5CSI interface 14-1 .
14-2 is known in advance, the SC8I interface control circuit 2 corresponding to the device number
Either one of 6-1 and 26-2 is selectively connected.

SC3I interface control circuit 26-1. 26-2
performs interface control according to the SC3I protocol.

FIG. 3 shows a transition diagram of the SC3I interface, and the 5C8I phase is Bus FREE.

^REBITRAT! ON, 5ELCTION,
RESELECTION, MESSAGEOUT,
COMMAND, DATAIN, DATA OUT
, 5TATUS, and MESSAGEIN phases. The arrows in FIG. 3 indicate directions in which phase transitions are possible.

Next, the method of phase transition will be explained using command execution as an example.

In 5C3I, when no command is executed, B
We are in the tlS FREE phase. At that time, in order to execute the command, it moves to the ^RB ITRATION phase to obtain the right to use the 5C3I BtlS. If you can get the usage rights here, 5ELECTI
Moving to the ON phase, the initiator who wishes to issue a command selects a target to execute the command. After this, the process moves to the MESSAGE 011T phase, and a message specifying which device under the selected target is to execute the command is sent from the initiator to the target. Through the above series of processes, the connection between the initiator, the target, and the devices under it is completed.

The target then moves to the COMMAND phase in which it receives and takes commands from the initiator. Here, the initiator sends a command to the target. The subsequent phase transition is divided into three depending on the type of command. The first type is a command that does not transfer data, and the command phase moves directly to the 5TATtlS phase. The second one is REQtlEST 5ENSE
It transfers data directly without any mechanical action like commands, and is used in I) ATA IN phase or DA
Move to TA OUT phase.

In the DATA IN phase, data is transferred from the target to the initiator, and in the DATA OUT phase, data is transferred from the initiator to the target. The direction of this data transfer is uniquely determined by the command. The third type involves a mechanical operation such as a seek before data transfer, during which a transition is made to the MESSAGE IN phase to break the bond between the initiator and target, and a message to break the bond is sent from the target to the initiator. send to As a result, the bus transitions to the BUS FREE phase.

Then, when the target completes the mechanical movement, it will combine with the initiator again to execute the command.
The target side moves to the RBITRATION phase and acquires the right to use 5C3I 8US.

Thereafter, the process moves to the RESELECTION phase to select an initiator from the target. After that M
The process moves to the ESSAGE IN phase and sends a message to the initiator to notify the initiator which device under the target is to resume commands. At this point, the initiator, target, and the device under it again communicate. The join is complete. After that, the DAT
A Transition to IN phase or DATAOUT phase to transfer data. After transferring data, 5T
Shifts to ATUS phase and notifies the initiator of the command execution results. After that, MESSAGE IN
phase and signal completion of the command. This completes one command. If a command is to be executed further, the process moves to the COMMAND phase and the process is repeated.

If you do not need to execute a command, use BusFRE
Move to E phase.

Next, the control operation according to the embodiment of FIG. 2 will be explained with reference to the operation flow diagram of FIG. 4.

First, when the system is powered on, the director 18 performs a system reset in step 81, and then in step S2.
run idle routine. Next, step S3
Go to and check if it is booted from CPUI O.
If activation has not been applied, the process proceeds to step S4, where it is determined from the device side whether or not there is glue selection. If there is no reselection in step S4, proceed to step S5,
It is determined from the information stored in the control memory 30 whether or not there is a device whose processing has been interrupted because it is busy, and if there is no device whose processing has been interrupted, the process returns to the idle routine of step S2 again and is repeated.

Assume that in a standby state in which the processes of steps 82 to $5 are repeated, the device 12-2 connected from the CPU 10 to the 5C8I interface 14-1 is activated. This startup command from the host 10 is determined in step S3, and the device number included in the input/output command from the CPU is sent to the director 18 in step S6.
The MPU 28 decodes the device number, and since the device 12-2 corresponding to the device number is on the SC8I interface 14-1 side, it controls the changeover switch 16, and in step S7
The CSR interface control circuit 26-1 side is selectively connected to the data transfer buffer 24 side, and in the next step S8, the director selects the device 12-2.

Subsequently, in step S9, the command sent from CPU10 is decoded, and in the command phase of step SIO, a 5csr command is sent to device 12-2.

Assuming that a read command is now sent from the CPU, when the device 12-2 receives the read command in the command phase of step SIQ, it starts a seek operation to position and move the head to the address track specified by the read command. Since it takes time to complete the seek, a disconnect message is sent to the director 18 as a message in phase in step S11, and the process returns to the idle routine in step S2 as a path free phase.

Subsequently, when the seek operation is completed in the device 12-2, data is read, and the read data is written into the buffer within the device 12-2, selection is performed on the director 18. The glue selection from this device 12-2 is determined in step S4, and step 81
Proceed to step 2.

Step S4: By determining the glue selection, Step S1
Proceeding to the message in phase 2, device 12-
2 sends an identification message and reconnects with the director 18 after disconnection. After this, changeover switch 16 to SC3I interface 14
Switch to -1 side. Subsequently, in step SI3, read data is transferred from the device 12-2 to the director 18 as a data phase, and the read data transferred to the director 18 and read data is transferred to the SC8I interface control circuit 26-1. Changeover switch 16. Data buffer 24°Channel interface controller 22. It passes through the driver receiver 20 and is sent to the main memory on the CPUI O side.

When the data transfer in step 813 is completed, step SI
4, the status information is sent from the device 12-2 to the director 18 as a status phase, and further step S
At I5, a command complete message is sent from the device 12 to the director 18 as a message in phase. The director 18, which has received the command complete message, checks the received status value in the status phase of step SI4, reports the end status to the CPU 10 in step S16, and ends the series of processing.

Next, in step SI7, it is determined whether or not there is a command chain, and if a command chain is specified, the process proceeds to step S9.
On the other hand, if no command chain is specified, the process returns to the idle routine of step S2.

The above control operation is performed by the SC connected to the device 12-2.
Although this relates only to the 8I interface 14-1 side, in the present invention, two S
Since the CSR interfaces 14-1 and 14-2 are provided, when the MPU 28 of the director 18 is operating on one interface bus, it always checks the status of the other interface bus.

In the operation flow diagram of FIG. 4, as shown in (2), the state of the other interface bus is checked at the break in the processing of one interface bus, and the interruption sequence shown in FIG. 5 is repeatedly executed.

The interrupt sequence for monitoring an interface bus that is disconnected from the director 18 of FIG.
First, in step S1, it is determined whether or not there is a reselection from the device side. If there is a reselection, the process proceeds to step S2, where an identifying message is sent from the device side as a message in phase, and this identifying message is received. The director 18 side sends an interruption message to the device as a message out phase in step S3 to put it in a standby state, and further interrupts reselection in step S4;
and the machine number of the interrupted device in control memory 3.
After being stored as 0, in step S5 the bus becomes free, and the series of processing ends.

Therefore, there is no need to use any of the devices 12-8 to 12-14 on the 5C8I interface 14-2 side, which are disconnected while the device 12-2 is connected to the director 18 in FIG. 2, for reconnection after disconnection. If a selection request is made, device 12-
When one process on the second side is completed and the process moves to the next one, the MPU 28 is in a phase switching state as shown in FIG. 4, for example.
Processing according to the interruption sequence shown in FIG. 5 is executed through the C8I interface control circuit 26-2.

Therefore, the control operation with the device 12-2 is completed and the process returns to the idle routine of step S2, and step 82
When the device whose processing was interrupted due to busyness is checked in step S5 while in the standby state where the processing from ~S5 is repeated, the device whose processing was interrupted due to the execution of the interruption sequence shown in FIG. 5 is stored in the control memory 30 as SC.
Since the 5C8I interface control circuit 26-2 exists on the side of the 8I interface 14-2, the process proceeds to step S7, where the selector switch 16 selects the 5C8I interface control circuit 26-2, and then, in step S8, the interrupt device stored in the control memory 30 is selected. Perform device selection based on machine number,
In this case, since command decoding from the CPU has already been completed, the process proceeds from step S8 to the data phase of step S13, as indicated by the broken line, and the interrupted sequence is restarted.

Note that the above embodiment connects two SC8I interfaces 14- to a single CPUI O via the director 18.
1.14-2 can be selectively connected to allow for selective connection of a system configuration in which 14 devices are connected. However, within the allowable device access time, two or more SC3I interfaces can be selectively connected. By doing so, the number of connected devices may be further increased.

Further, although the above embodiment takes as an example the SC3I interface in which the maximum number of connected devices is 8, the present invention is not limited to this, and the present invention is not limited to this, but can connect multiple devices in common to a single host device. The present invention can be applied in exactly the same way to lower-level interfaces that have a limited number of connected devices.

- By setting up a host device and selecting and connecting the corresponding interface according to the device number from the host device, a large number of devices can be connected to a single host device without being restricted by the number of interfaces that can be connected. This makes it possible to easily expand the system scale by increasing the number of connected devices.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention; Fig. 2 is a configuration diagram of an embodiment of the present invention; Fig. 3 is a transition diagram of the SC3I interface; Fig. 4 is an operational flow diagram of the present invention; Fig. 5 is a diagram of the present invention An explanatory diagram of the interruption sequence; FIG. 6 is a block diagram of the conventional system. [Effects of the Invention] As described above, according to the present invention, even if there is a restriction on the number of devices connected to a lower-level interface that connects a plurality of devices to a higher-level device, a plurality of devices can be connected to a higher-level device through a selection means. Lower interface, 10: Upper device (CPU) 12.12-1 to 17: Device 14-1.14-2: Lower interface (SC8I interface) 16: Selection means (selector switch) 18: Director 20 driver/receiver 22: Channel interface controller 24: Data transfer buffer 26-1.26-2: SCS I interface control circuit 28: MPU 30: Control Romory Bad Luck"Moon's Ifl Cup Signs Charming Chart Figure 5

Claims (2)

[Claims] (1) Multiple devices (12
), a plurality of lower-level interfaces (14-1,
14-2) and each lower interface (14-1
, 14-2) for a maximum of (N-1) devices (12)
and selecting means (16) for selectively connecting one of the lower-lower interfaces (14-1, 14-2) according to the device number from the host device (10). device connection method. (2) The lower interface (14-1, 14-2)
is an S that can connect up to 8 devices including the host device (10).
Claim 1 characterized in that it is a CSI interface.
Device connection method described in Description 1.