JPH0380492A - Storage device - Google Patents

Abstract

PURPOSE:To accelerate a processing speed by receiving a next access demand with the aid of a second access demand holding means and controlling it to an identical address while the access is executed with the aid of a memory. CONSTITUTION:Address registers 1 and 2 hold transferred address information and write data based on the control of control signals 14 - 16 and output address signals 11 and 12 and a data signal 13. Besides, the content of the signal 13 is stored at the address of the memory 7 corresponding to the signal 11 based on the control of a control signal 17. Then, when it is decided by a comparator 3 that the signals 11 and 12 coincide each other, a coincidence signal 18 is outputted. The signal 18 is inputted to a gate circuit 10 together with the signal 15 and an AND is outputted. Then, it is decided whether the recommencement of write is executed or not. At this time, an access demand signal 21 is received by access demand signal holding circuits 4 and 5. Since the processing is executed by receiving the signal 21 with the aid of one of the circuits 4 and 5 and receiving with the aid of the other while the access is executed by the memory 7, the processing speed is accelerated.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a memory device using semiconductor memory elements.

[Conventional technology]

Conventionally, in this type of storage device, as shown in FIG. 2, a write data register 8, an address register 22, and a request signal register 23 are connected to a first place device (not shown), and each write Data, address and access request signals are input and held, the outputs of write data register 8 and address register 22 are connected to the data input and address input of memory 7, respectively, and the output of request signal register 23 is connected to the control signal generation circuit. It was connected to 24 inputs. Control signal generation circuit 24 generates and outputs write control signals for write data register 8 and address register 22, and write/read control signals for memory 7. When a memory access request is made from a host device, the request signal register 23 first receives the access request and transmits it to the control signal generation circuit 24. The write data and address information are stored in the write data register 8 and address register 22, respectively, at a predetermined time after receiving the access request.
and the information is input into the memory 7.

On the other hand, the control signal generation circuit 24 uses the RAS necessary for the memory 7.
Control signals such as a signal, a CAS signal, and a write signal are provided to the memory 7. In this way, writing is executed to the address specified by the address report. Reading is also possible using the read register (
(not shown) is connected to the output terminal of the memory 7, and reading is controlled by the output of the control signal generation circuit 24.
It is executed similarly.

[Problem that the invention seeks to solve]

In the conventional storage device described above, a dynamic MO3 semiconductor memory is used as the storage element used in the memory 7, and its operating speed is slower than that of the logic element used in the host device. , the higher-level device cannot issue the next memory request until the series of operations for one memory request is completed, which has the disadvantage of slowing down the processing speed.

[Means for solving problems]

The storage device of the present invention includes a storage means for inputting a first address signal as an address, and an access request signal for requesting access to the storage means when the first and second admission control signals are at a first logic level. and outputs first and second control signals, respectively, and when the first and second admission control signals are at a second logic level, the reception of the access request signal is inhibited. 1 and 2nd access request A 33 holding means; and 1st and 2nd access request holding means that hold address information input to each and output first and second address signals under the control of the first and second control signals. a second address register; a comparison means for inputting the first and second address signals and outputting a match signal when the two match; and a comparison means for holding the input write data under the control of a third control signal. write data register to output to the storage means and/or data read from the storage means to the fourth register.
a read data register which is held and output under the control of the control signal of the first . The output of the second access request signal holding means and the output of the comparison means are input, and at the initial stage of operation, the first admission control signal of the first logic level and the second admission control signal of the second logic level are respectively input. 1 and a second access request signal holding means, and when the first control signal is input and the comparison means does not output a matching signal, the comparison means responds to the first control signal and outputs the second control signal. and when a coincidence signal is input, outputs the third/fourth control signal and a fifth control signal for controlling the writing/reading of the storage means in response to their AND, and also outputs the third/fourth control signal and a fifth control signal for controlling the writing/reading of the storage means. The control signal generation means outputs a first admission control signal at a second logic level and a second admission control signal at the first logic level until the access to is completed.

[For production]

In this way, while the first access request signal holding means accepts an access request and the memory is being accessed, the second access request signal holding means accepts the next access request and the control signal generating means By controlling access to the same address, the apparent cycle time of the storage device can be shortened and the processing speed of the storage device can be improved.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the storage device of the present invention.

Address register 1.2 and write data register 8
holds address information and write data transferred from a host device (not shown) under the control of control signals +4°I5 and 16, and outputs address signals 11, 12 and data signals 13, respectively. Memory 7 includes RAS,
Under the control of control signal +7 including CAS and write signals, data signal 13 is sent to the address corresponding to address signal 11.
The contents of are stored. Comparator 3 compares address signals 11 and 12, and outputs a match signal (11") when they match. Access request signal holding circuit 4 is composed of request signal register 4I and gate circuit 42. The gate circuit 42 inputs the access request signal 21 (-"l") and the admission control signal 19 transferred from the host device, and the request signal register 41 inputs the output of the gate circuit 42. When open, when the access request signal 21 is input, the control signal 14 of '1' is output. The access request signal holding circuit 5 is similarly configured by a request signal register 51 and a gate circuit 52, and outputs a control signal 15. The control signal generation circuit 6 generates the control signal 1
4.15 and the output 18 of the comparator 3 are input, and when the control signal 14 is "L", the output 18 of the comparator 3 is "
O'', the control signal 16 is activated in response to the control signal 14.
and 17, the control signal 15 and the output 1 of the comparator 3
8 are both °l", control signals 16 and 17 are output in response to their logical product, and acceptance control signals I9 and 20 are output as '0" and 20, respectively, until the access to the memory 7 is completed. Set it to “1”. Register 9 inputs and holds control signal 15. Gate circuit IO
inputs the control signal 15 and the output 18 of the comparator 3, and outputs their AND.

Next, the operation of this embodiment will be explained.

At the initial stage of operation, the reception control signals 19 and 20 are "■" and "0", respectively, and the access request signal 2
1 (~"l") passes through the gate circuit 42 and is sent to the request signal register 4. The address information is held in the control signal generating circuit 6 and the address register 1, and the address information is held in the address register 1. Further, the control signal generation circuit 6 generates a control signal 16 and applies it to the write data register, and the write data is held in the write data register 8. The address information and write data held in the address register 1 and the write data register 8 are input to the memory 7, and a predetermined control signal 17 is sent from the control signal generation circuit 6 to the memory 7 to execute writing. Further, acceptance of the next request signal is inhibited until the acceptance control signal 19 becomes "0" and the write operation of the memory 7 is completed.

Until the write operation of the memory 7 is completed, the admission control signal 20 becomes "L" and the gate circuit 52 is opened. If the access request signal 21 is transmitted at that time, it is held in the request signal register 5I. , are sent to the address register 2 and the control signal generation circuit 6. As a result, address information is held in the address register 2 and input to the comparator 3. Comparator 3 compares the contents of address register l and address register 2
The comparison results are input to the control signal generation circuit 6 and the gate circuit 10. If address registers 1 and 2
If the contents match 4, the write data is held in the write data register 8 again, a predetermined control signal 17 is output from the control signal generation circuit 6 to the memory 7, and the subsequent contents are written to the memory 7. be included. The output of the request signal register 5I is connected to the gate circuit IO via the register 9, and the output 18 of the comparator 3 is connected to the other input of the gate circuit 10. You can see if the process has been redone.

In this embodiment, a write request is transmitted again to the same address during a write operation, but a read operation during a write operation and a write operation during a read operation are also transmitted to the same address. can be controlled in the same way. In this case,
Connect the read data register to the output terminal of memory 7,
The control signal that controls writing/reading to the register is:
Similar to this embodiment, the control signal generation circuit 6 generates and outputs the signal.

〔Effect of the invention〕

As explained above, in the present invention, while an access request is accepted by the first access request signal holding means and the memory is being accessed, the second access request signal holding means accepts the next access request. By controlling access to the same address by the control signal generating means, there is an effect that the apparent cycle time of the storage device can be shortened and the processing speed of the storage device can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the storage device of the present invention, and FIG. 2 is a block diagram of a conventional example of this type of storage device. 1.2-・・・・・・・・・・・・Address register, 3・・・・・・・・・・・・・・・Comparator, 4, 5- −−−−−−−−・・Access request signal holding circuit, 4, . 5. ----------, -Request signal register, 4, . 52.10--Gate circuit, 6--------------- Control signal generation circuit, 7-- ---Memory, 8--------------Write data register, 9---------------- Register, 11.12, 13,14.15. -16.17
．． 18, 19. 20--Signal line, 21-------
−−−−−−−−−−Access request signal.

Claims (1)

[Scope of Claims] Storage means for inputting a first address signal as an address; and when the first and second admission control signals are at a first logic level, an access request signal for requesting access to the storage means; a first control signal that receives and holds the access request signal and outputs a first and second control signal, respectively, and inhibits acceptance of the access request signal when the first and second admission control signals are at a second logic level; and a second access request signal holding means; first and second access request signal holding means that hold address information input thereto and output first and second address signals under the control of the first and second control signals; an address register, a comparison means for inputting the first and second address signals and outputting a match signal when the two match, and holding and storing the input write data under the control of a third control signal. a write data register for outputting to the storage means; and/or a read data register for holding and outputting data read from the storage means under the control of a fourth control signal; and a first and second access request signal holding means. The output and the output of the comparison means are input, and at the initial stage of operation, the first admission control signal at the first logic level and the second admission control signal at the second logic level are held as the first and second access request signals, respectively. When the comparison means does not output a coincidence signal when the first control signal is input, the comparison means responds to the first control signal, inputs the second control signal, and inputs the coincidence signal. In response to the logical product, the third/fourth control signal and the fifth control signal for controlling the writing/reading of the storage means are output, and the second control signal is output until the access to the storage means is completed. A storage device comprising control signal generating means for outputting a first admission control signal at a logic level and a second admission control signal at a first logic level.