JPH0380495A - Sequential decoder - Google Patents

Abstract

PURPOSE:To contract a pattern area by alternately driving the data transfer gates of the odd and even stages in a serial register part in a preset state. CONSTITUTION:The serial register part 13 is constituted of plural stages each of which consists of an 1-bit delay circuit obtained by serially connecting a data transfer gate 21 and a presetable data inversion transfer circuit 22. The delay circuits are serially or loop-like connected as a whole and the data transfer gates 21 of the odd and even stages are alternately driven by data transfer clocks phi1, phi2. When the voltage impressed to both the ends of the circuit 22 in each stage in the register part 13 is applied to a decoder part 14, the decoder 12 generates a sequential output. Consequently, the pattern area can be contracted, and even if the number of sequential stages is increased, the increment of the pattern occupation area on an integrated circuit can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a sequential decoder used, for example, in a sequential access memory.

(Prior Art) FIGS. 9 and 10 show conventional examples of sequential decoders used in sequential access memories. That is, the sequential decoder shown in FIG. 9 has n sequential stages, and consists of n stages of D-type flip-flop circuits 90 . . . connected in series. Since this sequential decoder is placed at one end of the memory cell array, it is necessary to lay out the pattern of the D-type flip-flop circuit 90 in an area limited by the size (pitch) of the memory cells. However, since the D-type flip-flop circuit 90 has a complicated circuit configuration and uses a large number of elements, its butterfly area becomes large and the pattern becomes large in the direction perpendicular to the pitch direction of the memory cells.

On the other hand, in the sequential decoder shown in FIG. 10, the number of sequential stages is n, and the binary counter section 10 is composed of flip-flop circuits 91 of Nog2n stages.
0, and a decoder unit 10 that decodes the output signals (positive phase signal, negative phase signal) of each stage of this binary counter unit 100.
Consists of 1. In this sequential decoder, the number of stages 11og2n of the flip-flop circuits 91 is less than n, so the pattern layout of the flip-flop circuits 91 is not limited by the pitch of the memory cells. However, since a wiring area 102 is required to extract the output of the binary counter section 100 in a direction perpendicular to the pitch direction of the memory cells and input it to the decoder section 101, the sequential decoder described above is perpendicular to the pitch direction of the memory cells. The pattern becomes larger in the opposite direction. In particular, as the number of sequential stages n increases, more wiring is required between the binary counter section and the decoder section, the wiring area 102 increases significantly, and the area occupied by the pattern on the memory integrated circuit chip increases.

(Problem to be Solved by the Invention) As described above, in the conventional sequential decoder, when using the same number of D-type flip-flop circuits as the number of sequential stages, the pattern is In addition, when using a binary counter and a decoder, as the number of sequential stages increases, the wiring area between the binary counter section and the decoder section increases, and the area occupied by the pattern on the memory integrated circuit chip increases. There is a problem.

The present invention has been made to solve the above-mentioned problems, and its purpose is to provide a sequential decoder that can reduce the pattern area and prevent the pattern area on an integrated circuit chip from increasing even if the number of sequential stages increases. Our goal is to provide the following.

[Structure of the Invention] (Means for Solving the Problems) In the sequential decoder of the present invention, a 1-bit delay circuit in which a data transfer gate and a presettable data inversion transfer circuit are serially connected is used in each stage,
This 1-bit delay circuit is connected in series or in a loop as a whole, and includes a serial register section in which odd-numbered stage data transfer gates and even-numbered stage data transfer gates are alternately driven by a data transfer clock, and this serial register section. The present invention is characterized in that it includes a decoder section that receives voltages across the data inversion and transfer circuits of each stage and decodes the data to generate sequential outputs.

(Function) In the initial state, the data inversion transfer circuits in each stage of the serial register section are preset to the desired data state, and then the data transfer gates in the odd-numbered stages and the data in the even-numbered stages of the serial register section are preset to the desired data state. By driving the transfer gates alternately, the outputs of each stage of the decoder section are sequentially turned on, and an output signal for sequential access is generated.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 schematically shows the configuration of a sequential access memory, where 10 is a memory cell array, 11 is a row decoder that decodes a row address signal, and 12 is a sequential decoder placed at one end of the memory cell array 10. . This sequential decoder 12 is
Serial register section 13 and this serial register section 1
The decoder section 14 receives the outputs from each stage of 3 and decodes them to generate sequential outputs.

In the memory cell array IO, row selection is performed by the output of the a-u decoder 11, and column selection is performed by the sequential output of the sequential decoder 12.

Note that the row selection is performed by the sequential output of the sequential decoder 12, and the column decoder (not shown)
Column selection may be performed based on the output of .

FIG. 2 shows an example of the sequential decoder 12 in FIG. 1. The serial register section 13 is
A 1-bit delay circuit in which a data transfer gate 21 and a presettable data inversion transfer circuit 22 are serially connected is used in each stage, and the 1-bit delay circuit as a whole is serially connected. Then, a set signal Set for presetting, a reset signal Re5et
and a data transfer clock are applied, and the data transfer gates 21 in odd-numbered stages and the data transfer gates 21 in even-numbered stages are alternately driven by the data transfer clock.

Here, as the data transfer gate 21, for example, a CMOS
A transfer gate (consisting of an N-channel transistor TN and a P-channel transistor TP connected in parallel) is used, and clocks (φ1, φ2) and their inverted clock (φ11) are used as data transfer clocks.
φ2) is given. These clocks φ15φ2 are complementary signals with mutually opposite phases or two-phase signals that do not overlap each other, and are used in odd-numbered CMOS transfer gates 21.
Clock φ11φl is applied corresponding to each gate of the N-channel transistor and P-channel transistor of Given.

Note that when the set signal Set for presetting is input to the serial register unit 13, the input of the clock for data transfer is prohibited by the prohibition gate circuit 23, and this prohibition gate circuit 23 is configured to input the reset signal Re5et.
Prohibition is controlled by

The data inversion transfer circuits 22 in the first stage and the even number stages in the serial register section 13 are each configured as shown in FIG. , respectively, for example in Figure 3 (
It is configured as shown in b).

That is, in FIG. 3(a), 31 is P for presetting.
A channel transistor 32 is a data inversion holding circuit. The data inversion/holding circuit 32 is formed by, for example, an inverter 34 connected in feedback between the output terminal and the input terminal of an inverter 33. The source of the P-channel transistor 31 for presetting is connected to the power supply potential Vcc, and the input terminal of the data inverting and holding circuit 32 is connected to the drain of the P-channel transistor 31.

In FIG. 3(b), 35 is an N-channel transistor for presetting, and 32 is a data inversion/holding circuit. The source of the N-channel transistor 35 for presetting is connected to the ground potential VSS, and the drain of the N-channel transistor 35 is connected to the input terminal A of the data inversion/holding circuit 32.

In the data inversion/holding circuit 32, the output of the feedback inverter 34 is connected to the previous CMOS transfer gate 2.
In order to reduce the effect of collision with the output of 1 (this,
The mutual conductance gmz of the feedback inverter 34 is designed to be smaller than the mutual conductance gm1 of the inverter 33 connected in the forward direction.

A set signal Set is applied to the gates of the N-channel transistors 35 for presetting in each stage of the serial register section 13, and an inverted signal of the set signal Set is applied to the gates of the P-channel transistors 31 for presetting in each stage. A reset signal Re5et is applied.

In addition, the first stage of the serial register section 13 is CMOS)
One end of the transfer gate 21 is connected to the ground potential VSS, and in each stage except the first stage, one end of the CMOS transfer gate 21 is connected to the output terminal B of the data inversion holding circuit 32 in the previous stage.
It is connected to the.

On the other hand, the decoder section 14
For each stage, one end and the other end of each CMOS transfer gate 21 are input to two-man NOR gates 16 to obtain decoded outputs Si and Si+1.

In this case, since the configuration is such that the voltage (normal rotation, inversion) at both ends of the data inversion transfer circuit 22 of each stage of the serial register unit 13 is taken out and decoded, the number of gates in the decoder unit 14 is has been reduced.

Next, the operation of the sequential decoder shown in FIG. 2 will be explained with reference to FIG. 4. FIG. 4 shows how the data at the input terminal A and the data at the output terminal B of the data inverting and holding circuit 32 of each stage of the serial register section 13 are shifted.

In the initial state where the set signal Set for presetting is manually input (becomes 1 degree level), the clocks φ1 and φ2
is "Q II," the inversion clock φ1.7 becomes "1 degree," and the CMOS transfer gates 21 are all turned off. At this time, the presetting N-channel transistor 35...
are all turned on, and the reset signal Re5 at “0” level
P-channel transistor 3 for presetting by et
1... are all turned on. As a result, the data inversion holding circuits 3 of the first stage and even stages of the serial register section 13
2... is a state in which input terminal AJ (1#, output terminal B is "0"), and data inversion/holding circuits 32 of odd-numbered stages except the first stage are in a state where input terminal A is 01 and output terminal B is 1". is preset to .

In this initial state, the inputs of the NOR gates 16 of each stage of the decoder section 14 are inputted by at least one of the inputs "
1'', the decoded output St is all “0”.

Next, in step 1, if φ2 is set to "1" and φ1 is set to '0', then in the even numbered stages of the serial register section 13, CMOS)
The transfer gates 21... are turned on and the transfer data from the previous stage is taken into the data inversion/holding circuits 32..., but in odd-numbered stages, the CMOS transfer gates 21...
remains off, so its data does not change. As a result, the human power of the NOR gate 16 at the first stage of the decoder section 14 becomes O", so that the decoded output S1 of the decoder section 14 becomes '1m.

Next, in step 2, if φl is set to "1" and φ2 is set to "O", then in the odd numbered stages of the serial register section 13, 0MO8)
The transfer gates 21... turn on and take in the transfer data from the previous stage (the first stage takes in "0°"), but in the even stages, the CMOS) transfer gates 21... remain off. Therefore, the data does not change.As a result, the inputs of the second stage NOR gate 16 of the decoder section 14 both become "02", so the decoded output S2 of the decoder section 14 becomes "02".
becomes “1°.

After step 3, the same operations as those in steps 1 and 2 described above are repeated, and the decoded outputs S3 and after of the decoder section 14 sequentially become "1".

According to the sequential decoder of the above embodiment, one data transfer gate 21, one presettable data inversion transfer circuit 22, and one decoding gate 16 are formed in each stage in an area limited by the pitch of memory cells. In this case, since the configuration of each circuit is simple and the number of elements used is small, the pattern layout of the D-type flip-flop circuit 90 is performed in an area limited by the pitch of memory cells, as in the conventional example shown in FIG. The pattern area is reduced by about 20 to 30% compared to the case where it is necessary. In addition, since the number of wires between the serial register section 13 and the decoder section 14 is small, the wiring area 102 between the binary counter section and the decoder section becomes smaller as the number of sequential stages increases, as in the conventional example shown in FIG. There is no problem that the area occupied by the pattern on the memory integrated circuit chip increases.

FIGS. 5(a) to 5(1) show modifications of the brisé-tuple data inversion transfer circuit shown in FIG. 3(a) or (b), respectively.

i5 The data inversion transfer circuit shown in FIGS. 3(a) and 3(b) is different from the data inversion transfer circuit shown in FIG. Vss and data inversion holding circuit 3
2, and the gate control signals of the presetting transistors 31 and 35 are changed.

The data inversion and transfer circuits shown in FIGS. 5(c) and 5(d) are different from the data inversion and transfer circuit shown in FIG. 3(a) or (b) by omitting the presetting transistors 31 and 35 and Inverter 33 or 34 of inversion holding circuit 32
Either one of the gates is changed to a two-man gate 51, and the set signal Set or the reset signal Re5et is applied as the human power of one of the gates 51.

Compared to the data inversion transfer circuit shown in FIG. 3(a) or (b), the data inversion transfer circuit shown in FIGS. 5(e) and (f) omits the presetting transistors 31 and 35, Inverter 33 or 34 of holding circuit 32
Either one of them is changed to a two-man NAND gate 52, and the set signal Se is input as one input of this NAND gate 52.
t or a reset signal Re5et is applied.

The data inversion transfer circuits in FIGS. 5(g) to (j)
Compared to the data inversion transfer circuit shown in FIG.
4 is changed to a composite gate consisting of a two-man power gate 53 and a two-man power gate 54 or a two-man power OR gate 55 and a two-man power gate 56, and a set signal Set or a reset signal Re5et is applied to this composite gate. It has been changed to give Here, the data inversion transfer circuits in FIGS. 5(g) and (j) are reset priority circuits, and the data inversion transfer circuits in FIGS. 5(h) and (1) are set priority circuits.

The data inversion transfer circuit of FIG. 5(k) is different from the data inversion transfer circuit shown in FIG. Instead, it is modified so that only one inverter 57 is used to dynamically hold data.

The data inversion transfer circuit of FIG. 5(1) is different from the data inversion transfer circuit shown in FIG. This is modified so that data is held dynamically using only one inverter 58, and the voltage obtained by inverting the output terminal voltage of this inverter 58 by five inverters and the input terminal voltage of the inverter 58 is used as a decoder. This is modified so that the signal is input to the NOR gate 16 of the corresponding stage of the section 14.

6(a) to 6(d) each show an example in which the data transfer gate 21 of the serial register section 13 shown in FIG. 2 is modified. That is, in FIG. 6(a), the clock φl or φ2 is applied to the gate of the N-channel transistor 61. Also, Fig. 6(b)
In this example, the inverted clock φ1 or φ2 is applied to the gate of the P-channel transistor 62.

In addition, in FIG. 6(C), the N-channel transistor 63
The clock φ1 is applied to the gate of the P-channel transistor 64, and the inverted clock φ2 is applied to the gate of the P-channel transistor 64. Further, in FIG. 6(d), the inverted clock <6+ is applied to the gate of the P-channel transistor 65, and the clock φ2 is applied to the gate of the N-channel transistor 66.

7(a) to 7(d) each show an example in which the decoder section 14 of the sequential decoder 12 shown in FIG. 2 is modified. That is, in FIG. 7(a), the two-person gate 16 in FIG. 2 is changed to a three-person gate 71, and the decoding stop control signal STP is provided as one input of this NOR gate 71. When this signal S'TP is "11", the NOR gate 7 of the decoder section
All outputs of 1 become 'Om', and the column of the memory cell array becomes unselected.

In addition, in FIG. 7(b), the two-person gate 16 in FIG. 2 is changed to a three-input NAND gate 72, and one input of this NAND gate 72 is the decoding stop control signal
The modification is made so that an inverted signal STP of P is provided. When this inverted signal STP is "0", all the outputs of the Nant gates 72 in the decoder section become "1", and the column of the memory cell array becomes unselected.

In addition, in FIG. 7(C), the voltage obtained by inverting the input terminal voltage of the even-numbered data inverting transfer circuits 22 of the serial register section l3 by the inverter 73 and the output terminal voltage of the preceding stage data inverting transfer circuit 22 are converted into a decoder. A voltage obtained by inverting the output terminal voltage of the even-numbered stage data inversion transfer circuit 22 of the serial register section 13 by the inverter 73 and the input terminal of the subsequent stage data inversion transfer circuit 22 are input to the three-person gate 74 of the even-numbered stages of the serial register section 14. The decoding stop control signal STP is supplied as a manual input to one of these NOR gates 74.

In addition, in FIG. 7(d), the voltage obtained by inverting the input terminal voltage of the odd-numbered data inverting transfer circuits 22 of the serial register unit 13 by the inverter 75 and the output terminal voltage of the preceding stage data inverting transfer circuit 22 are converted into a decoder. It is input to the odd-numbered NAND gate 76 of the serial register section 14.
The voltage obtained by inverting the output terminal voltage of the data inverting transfer circuit 22 in the odd numbered stages by the inverter 75 and the input terminal voltage of the data inverting transfer circuit 22 in the subsequent stage are input to the three-input NAND gate 76 in the even numbered stages of the decoder section 14. , and an inverted signal STP of the decoding stop control signal STP is provided as one input of these Nant gates 76.

FIG. 8 shows the sequential decoder 12 shown in FIG.
This shows an example of a modified serial register section 13 of
The difference is that the serial register section 13 is connected in a loop so that the data output of the last stage becomes the data output of the first stage.

If such a loop-shaped serial register section 13 is used, as long as the necessary clock for transfer control continues to be manually operated,
Decode output Si is S1 to Sn.

Shifts are repeated in the order of S1%...

[Effects of the Invention] As described above, according to the sequential decoder of the present invention, the pattern area can be reduced, and even if the number of sequential stages increases, the area occupied by the pattern on the integrated circuit chip can be prevented from increasing.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing an example of a sequential access memory according to an application example of the sequential decoder of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the sequential decoder in FIG. 1, and FIG. Figure 3 (a)
is a circuit diagram showing an example of a presettable data inversion transfer circuit of the first stage and even numbered stages in the serial register section in FIG. 2, and FIG. FIG. 4 is a circuit diagram showing an example of a presettable data inversion transfer circuit, and FIG. 4 is a circuit diagram showing an example of a presettable data inversion transfer circuit. A diagram showing how the data shifts,
FIGS. 5(a) to (1) are circuit diagrams showing modifications of the presettable data inversion transfer circuit shown in FIG. 7(a) to 7(d) are circuit diagrams showing modified examples of the data transfer gate of the serial register section shown in FIG. 2, respectively.
) are a circuit diagram showing a modified example of the decoder section of the sequential decoder shown in FIG. 2, FIG. 8 is a block diagram showing a modified example of the serial register section of the sequential decoder shown in FIG. 2, and FIG. 1 and 10 are circuit diagrams showing conventional sequential decoders, respectively. 10... Memory cell array, 11...
Row decoder, 12... Sequential decoder, 13... Serial register section, 14...
...Decoder section, 16.71.72.74.76...
...Decoding gate, 21...CMOS
Transfer gate (data transfer gate), 22...
...Presettable data inversion transfer circuit, 31.3
5...Transistor for presetting, 32...
...Data inversion holding circuit, φ1. φ2. φ1. φ2
······clock.

Claims (2)

[Claims] (1) A 1-bit delay circuit consisting of a data transfer gate and a presettable data inversion transfer circuit connected in series is used in each stage, and this 1-bit delay circuit is connected serially or in a loop as a whole, and an odd number of stages A serial register section in which the data transfer gates of the even-numbered stages and the data transfer gates of the even-numbered stages are driven alternately by a data transfer clock, and a voltage across the data inversion transfer circuit of each stage of this serial register section is applied to produce a sequential output. 1. A sequential decoder comprising: a decoder unit that decodes data in such a manner that the sequential decoding occurs. (2) The sequential decoder according to claim 1, wherein the sequential decoder is used for row selection or column selection of a sequential access memory.